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[src/trunk]: src/sys/arch/arm/arm Add sa11x0_context_switch and sa11x0_drain_...



details:   https://anonhg.NetBSD.org/src/rev/504717004cc0
branches:  trunk
changeset: 526434:504717004cc0
user:      rjs <rjs%NetBSD.org@localhost>
date:      Fri May 03 12:43:53 2002 +0000

description:
Add sa11x0_context_switch and sa11x0_drain_readbuf.

Reviewed by Ben Harris and Jason Thorpe.

diffstat:

 sys/arch/arm/arm/cpufunc_asm_sa11x0.S |  30 +++++++++++++++++++++++++++++-
 1 files changed, 29 insertions(+), 1 deletions(-)

diffs (43 lines):

diff -r d7437101ee84 -r 504717004cc0 sys/arch/arm/arm/cpufunc_asm_sa11x0.S
--- a/sys/arch/arm/arm/cpufunc_asm_sa11x0.S     Fri May 03 12:12:03 2002 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_sa11x0.S     Fri May 03 12:43:53 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_sa11x0.S,v 1.1 2002/01/30 00:25:08 thorpej Exp $   */
+/*     $NetBSD: cpufunc_asm_sa11x0.S,v 1.2 2002/05/03 12:43:53 rjs Exp $       */
 
 /*
  * Copyright (c) 2002 Wasabi Systems, Inc.
@@ -93,5 +93,33 @@
 
        /* Restore interrupts (which will cause them to be serviced). */
        msr     cpsr_all, r3
+       mov     pc, lr
 
+
+/*
+ * This function is the same as sa110_context_switch for now, the plan
+ * is to make use of the process id register to avoid cache flushes.
+ */
+ENTRY(sa11x0_context_switch)
+       /*
+        * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
+        * Thus the data cache will contain only kernel data and the
+        * instruction cache will contain only kernel code, and all
+        * kernel mappings are shared by all processes.
+        */
+
+       /* Write the TTB */
+       mcr     p15, 0, r0, c2, c0, 0
+
+       /* If we have updated the TTB we must flush the TLB */
+       mcr     p15, 0, r0, c8, c7, 0   /* flush the I+D tlb */
+
+       /* Make sure that pipeline is emptied */
+       mov     r0, r0
+       mov     r0, r0
        mov     pc, lr
+
+ENTRY(sa11x0_drain_readbuf)
+       mcr     p15, 0, r0, c9, c0, 0           /* drain read buffer */
+       mov     pc, lr
+



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