[src/trunk]: src/sys/arch/arm/arm Shave an instruction off the case where we ...

[thorpej <thorpej%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/7ef65358e81f
branches:  trunk
changeset: 521154:7ef65358e81f
user:      thorpej <thorpej%NetBSD.org@localhost>
date:      Thu Jan 24 17:53:08 2002 +0000

description:
Shave an instruction off the case where we want to do a CPWAIT and
then return.

diffstat:

 sys/arch/arm/arm/cpufunc_asm_xscale.S |  72 ++++++++++++----------------------
 1 files changed, 26 insertions(+), 46 deletions(-)

diffs (189 lines):

diff -r d1d3c89c05d6 -r 7ef65358e81f sys/arch/arm/arm/cpufunc_asm_xscale.S
--- a/sys/arch/arm/arm/cpufunc_asm_xscale.S     Thu Jan 24 16:50:34 2002 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_xscale.S     Thu Jan 24 17:53:08 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_xscale.S,v 1.10 2002/01/24 06:21:27 thorpej Exp $  */
+/*     $NetBSD: cpufunc_asm_xscale.S,v 1.11 2002/01/24 17:53:08 thorpej Exp $  */
 
 /*
  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -96,9 +96,15 @@
        mov     tmp, tmp                /* wait for it to complete */   ;\
        CPWAIT_BRANCH                   /* branch to next insn */
 
+#define        CPWAIT_AND_RETURN_SHIFTER       lsr #32
+
+#define        CPWAIT_AND_RETURN(tmp)                                           \
+       mrc     p15, 0, tmp, c2, c0, 0  /* arbitrary read of CP15 */    ;\
+       /* Wait for it to complete and branch to the return address */   \
+       sub     pc, lr, tmp, CPWAIT_AND_RETURN_SHIFTER
+
 ENTRY(xscale_cpwait)
-       CPWAIT(r0)
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 /*
  * We need a separate cpu_control() entry point, since we have to
@@ -115,9 +121,7 @@
        mcrne   p15, 0, r2, c1, c0, 0   /* Write new control register */
        mov     r0, r3                  /* Return old value */
 
-       CPWAIT(r1)
-
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r1)
 
 /*
  * Functions to set the MMU Translation Table Base register
@@ -179,23 +183,19 @@
  */
 ENTRY(xscale_cache_flushID)
        mcr     p15, 0, r0, c7, c7, 0   /* flush I+D cache */
-       CPWAIT(r0)
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 ENTRY(xscale_cache_flushI)
        mcr     p15, 0, r0, c7, c5, 0   /* flush I cache */
-       CPWAIT(r0)
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 ENTRY(xscale_cache_flushD)
        mcr     p15, 0, r0, c7, c6, 0   /* flush D cache */
-       CPWAIT(r0)
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 ENTRY(xscale_cache_flushI_SE)
        mcr     p15, 0, r0, c7, c5, 1   /* flush I cache single entry */
-       CPWAIT(r0)
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 ENTRY(xscale_cache_flushD_SE)
        /*
@@ -205,13 +205,11 @@
         */
        mcr     p15, 0, r0, c7, c10, 1
        mcr     p15, 0, r0, c7, c6, 1   /* flush D cache single entry */
-       CPWAIT(r0)
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 ENTRY(xscale_cache_cleanD_E)
        mcr     p15, 0, r0, c7, c10, 1  /* clean D cache entry */
-       CPWAIT(r0)
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 /*
  * Information for the XScale cache clean/purge functions:
@@ -341,16 +339,14 @@
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
        mcr     p15, 0, r0, c7, c5, 1   /* flush I cache single entry */
        mcr     p15, 0, r0, c7, c6, 1   /* flush D cache single entry */
-       CPWAIT(r1)
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r1)
 
 ENTRY(xscale_cache_purgeD_E)
        mcr     p15, 0, r0, c7, c10, 1  /* clean D cache entry */
        CPWAIT(r1)
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
        mcr     p15, 0, r0, c7, c6, 1   /* flush D cache single entry */
-       CPWAIT(r1)
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r1)
 
 /*
  * Soft functions
@@ -375,9 +371,7 @@
 
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
 
-       CPWAIT(r0)
-
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 ENTRY(xscale_cache_purgeID_rng)
        cmp     r1, #0x4000
@@ -398,9 +392,7 @@
 
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
 
-       CPWAIT(r0)
-
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 ENTRY(xscale_cache_purgeD_rng)
        cmp     r1, #0x4000
@@ -420,9 +412,7 @@
 
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
 
-       CPWAIT(r0)
-
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 ENTRY(xscale_cache_syncI_rng)
        cmp     r1, #0x4000
@@ -442,9 +432,7 @@
 
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
 
-       CPWAIT(r0)
-
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 /* Used in write-through mode. */
 ENTRY(xscale_cache_flushID_rng)
@@ -463,9 +451,7 @@
 
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
 
-       CPWAIT(r0)
-
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 /* Used in write-though mode. */
 ENTRY(xscale_cache_flushD_rng)
@@ -483,9 +469,7 @@
 
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
 
-       CPWAIT(r0)
-
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 /* Used in write-through mode. */
 ENTRY(xscale_cache_flushI_rng)
@@ -503,9 +487,7 @@
 
        mcr     p15, 0, r0, c7, c10, 4  /* drain write buffer */
 
-       CPWAIT(r0)
-
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 /*
  * Context switch.
@@ -530,9 +512,7 @@
        /* If we have updated the TTB we must flush the TLB */
        mcr     p15, 0, r0, c8, c7, 0   /* flush the I+D tlb */
 
-       CPWAIT(r0)
-
-       mov     pc, lr
+       CPWAIT_AND_RETURN(r0)
 
 /*
  * xscale_cpusleep