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[src/trunk]: src/sys/arch/mips Add support for R5k secondary caches, from cod...
details: https://anonhg.NetBSD.org/src/rev/6e8ec0dc5271
branches: trunk
changeset: 544002:6e8ec0dc5271
user: rafal <rafal%NetBSD.org@localhost>
date: Sat Mar 08 04:43:24 2003 +0000
description:
Add support for R5k secondary caches, from code Chris Sekiya sent me a long
time ago, with small tweaks by me. Since the R5k doesn't do VCE, the pmap
still needs to be whacked for R5kSC CPUs to work correctly, but this is a
start.
diffstat:
sys/arch/mips/conf/files.mips | 3 +-
sys/arch/mips/include/cache_r4k.h | 25 +-----------
sys/arch/mips/include/cache_r5k.h | 71 ++++++++++++++++++++++++++++++++++
sys/arch/mips/mips/cache.c | 24 ++++++++--
sys/arch/mips/mips/cache_r5k.c | 57 ++++++++++++++++++++++++++-
sys/arch/mips/mips/cache_r5k_subr.S | 77 +++++++++++++++++++++++++++++++++++++
6 files changed, 225 insertions(+), 32 deletions(-)
diffs (truncated from 339 to 300 lines):
diff -r 11388be9bcf3 -r 6e8ec0dc5271 sys/arch/mips/conf/files.mips
--- a/sys/arch/mips/conf/files.mips Sat Mar 08 02:58:55 2003 +0000
+++ b/sys/arch/mips/conf/files.mips Sat Mar 08 04:43:24 2003 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.mips,v 1.45 2002/11/15 01:02:49 simonb Exp $
+# $NetBSD: files.mips,v 1.46 2003/03/08 04:43:25 rafal Exp $
#
defflag opt_cputype.h NOFPU
@@ -45,6 +45,7 @@
file arch/mips/mips/cache_tx39_subr.S mips1 & enable_mips_tx3900
file arch/mips/mips/cache_r4k.c mips3 | mips4
file arch/mips/mips/cache_r5k.c mips3 | mips4
+file arch/mips/mips/cache_r5k_subr.S mips3 | mips4
file arch/mips/mips/cache_r5900.c mips3 & mips3_5900
file arch/mips/mips/cache_mipsNN.c mips32 | mips64
diff -r 11388be9bcf3 -r 6e8ec0dc5271 sys/arch/mips/include/cache_r4k.h
--- a/sys/arch/mips/include/cache_r4k.h Sat Mar 08 02:58:55 2003 +0000
+++ b/sys/arch/mips/include/cache_r4k.h Sat Mar 08 04:43:24 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_r4k.h,v 1.9 2003/02/17 11:35:02 simonb Exp $ */
+/* $NetBSD: cache_r4k.h,v 1.10 2003/03/08 04:43:26 rafal Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -357,29 +357,6 @@
void r4k_pdcache_inv_range_32(vaddr_t, vsize_t);
void r4k_pdcache_wb_range_32(vaddr_t, vsize_t);
-void r5k_icache_sync_all_32(void);
-void r5k_icache_sync_range_32(vaddr_t, vsize_t);
-void r5k_icache_sync_range_index_32(vaddr_t, vsize_t);
-
-void r5k_pdcache_wbinv_all_16(void);
-void r5k_pdcache_wbinv_all_32(void);
-void r4600v1_pdcache_wbinv_range_32(vaddr_t, vsize_t);
-void r4600v2_pdcache_wbinv_range_32(vaddr_t, vsize_t);
-void vr4131v1_pdcache_wbinv_range_16(vaddr_t, vsize_t);
-void r5k_pdcache_wbinv_range_16(vaddr_t, vsize_t);
-void r5k_pdcache_wbinv_range_32(vaddr_t, vsize_t);
-void r5k_pdcache_wbinv_range_index_16(vaddr_t, vsize_t);
-void r5k_pdcache_wbinv_range_index_32(vaddr_t, vsize_t);
-
-void r4600v1_pdcache_inv_range_32(vaddr_t, vsize_t);
-void r4600v2_pdcache_inv_range_32(vaddr_t, vsize_t);
-void r5k_pdcache_inv_range_16(vaddr_t, vsize_t);
-void r5k_pdcache_inv_range_32(vaddr_t, vsize_t);
-void r4600v1_pdcache_wb_range_32(vaddr_t, vsize_t);
-void r4600v2_pdcache_wb_range_32(vaddr_t, vsize_t);
-void r5k_pdcache_wb_range_16(vaddr_t, vsize_t);
-void r5k_pdcache_wb_range_32(vaddr_t, vsize_t);
-
void r4k_sdcache_wbinv_all_32(void);
void r4k_sdcache_wbinv_range_32(vaddr_t, vsize_t);
void r4k_sdcache_wbinv_range_index_32(vaddr_t, vsize_t);
diff -r 11388be9bcf3 -r 6e8ec0dc5271 sys/arch/mips/include/cache_r5k.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/include/cache_r5k.h Sat Mar 08 04:43:24 2003 +0000
@@ -0,0 +1,71 @@
+/* $NetBSD: cache_r5k.h,v 1.1 2003/03/08 04:43:26 rafal Exp $ */
+
+/*
+ * Copyright 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if defined(_KERNEL) && !defined(_LOCORE)
+
+void r5k_icache_sync_all_32(void);
+void r5k_icache_sync_range_32(vaddr_t, vsize_t);
+void r5k_icache_sync_range_index_32(vaddr_t, vsize_t);
+
+void r5k_pdcache_wbinv_all_16(void);
+void r5k_pdcache_wbinv_all_32(void);
+void r4600v1_pdcache_wbinv_range_32(vaddr_t, vsize_t);
+void r4600v2_pdcache_wbinv_range_32(vaddr_t, vsize_t);
+void vr4131v1_pdcache_wbinv_range_16(vaddr_t, vsize_t);
+void r5k_pdcache_wbinv_range_16(vaddr_t, vsize_t);
+void r5k_pdcache_wbinv_range_32(vaddr_t, vsize_t);
+void r5k_pdcache_wbinv_range_index_16(vaddr_t, vsize_t);
+void r5k_pdcache_wbinv_range_index_32(vaddr_t, vsize_t);
+
+void r4600v1_pdcache_inv_range_32(vaddr_t, vsize_t);
+void r4600v2_pdcache_inv_range_32(vaddr_t, vsize_t);
+void r5k_pdcache_inv_range_16(vaddr_t, vsize_t);
+void r5k_pdcache_inv_range_32(vaddr_t, vsize_t);
+void r4600v1_pdcache_wb_range_32(vaddr_t, vsize_t);
+void r4600v2_pdcache_wb_range_32(vaddr_t, vsize_t);
+void r5k_pdcache_wb_range_16(vaddr_t, vsize_t);
+void r5k_pdcache_wb_range_32(vaddr_t, vsize_t);
+
+void r5k_enable_sdcache(void);
+
+void r5k_sdcache_wbinv_all(void);
+void r5k_sdcache_wbinv_range(vaddr_t, vsize_t);
+void r5k_sdcache_wbinv_rangeall(vaddr_t, vsize_t);
+void r5k_sdcache_inv_range(vaddr_t, vsize_t);
+void r5k_sdcache_wb_range(vaddr_t, vsize_t);
+
+#endif /* _KERNEL && !_LOCORE */
diff -r 11388be9bcf3 -r 6e8ec0dc5271 sys/arch/mips/mips/cache.c
--- a/sys/arch/mips/mips/cache.c Sat Mar 08 02:58:55 2003 +0000
+++ b/sys/arch/mips/mips/cache.c Sat Mar 08 04:43:24 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.c,v 1.17 2003/02/07 17:38:48 cgd Exp $ */
+/* $NetBSD: cache.c,v 1.18 2003/03/08 04:43:24 rafal Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -81,7 +81,8 @@
#endif
#ifdef MIPS3_PLUS
-#include <mips/cache_r4k.h> /* includes r5k and greater */
+#include <mips/cache_r4k.h>
+#include <mips/cache_r5k.h>
#endif
#if defined(MIPS32) || defined(MIPS64)
@@ -643,10 +644,6 @@
#ifdef ENABLE_MIPS_R4700
case MIPS_R4700:
#endif
-#ifndef ENABLE_MIPS_R3NKK
- case MIPS_R5000:
-#endif
- case MIPS_RM5200:
switch (mips_sdcache_ways) {
case 1:
switch (mips_sdcache_line_size) {
@@ -701,6 +698,21 @@
mips_sdcache_ways, mips_sdcache_line_size);
}
break;
+#ifndef ENABLE_MIPS_R3NKK
+ case MIPS_R5000:
+#endif
+ case MIPS_RM5200:
+ mips_cache_ops.mco_sdcache_wbinv_all =
+ r5k_sdcache_wbinv_all;
+ mips_cache_ops.mco_sdcache_wbinv_range =
+ r5k_sdcache_wbinv_range;
+ mips_cache_ops.mco_sdcache_wbinv_range_index =
+ r5k_sdcache_wbinv_rangeall; /* XXX? */
+ mips_cache_ops.mco_sdcache_inv_range =
+ r5k_sdcache_wbinv_range;
+ mips_cache_ops.mco_sdcache_wb_range =
+ r5k_sdcache_wb_range;
+ break;
#endif /* MIPS3 || MIPS4 */
default:
diff -r 11388be9bcf3 -r 6e8ec0dc5271 sys/arch/mips/mips/cache_r5k.c
--- a/sys/arch/mips/mips/cache_r5k.c Sat Mar 08 02:58:55 2003 +0000
+++ b/sys/arch/mips/mips/cache_r5k.c Sat Mar 08 04:43:24 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_r5k.c,v 1.7 2003/02/17 12:32:13 simonb Exp $ */
+/* $NetBSD: cache_r5k.c,v 1.8 2003/03/08 04:43:25 rafal Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -39,6 +39,7 @@
#include <mips/cache.h>
#include <mips/cache_r4k.h>
+#include <mips/cache_r5k.h>
#include <mips/locore.h>
/*
@@ -581,3 +582,57 @@
#undef trunc_line16
#undef round_line
#undef trunc_line
+
+/*
+ * Cache operations for R5000-style secondary caches:
+ *
+ * - Direct-mapped
+ * - Write-through
+ * - Physically indexed, physically tagged
+ *
+ */
+
+
+__asm(".set mips3");
+
+#define R5K_Page_Invalidate_S 0x17
+
+void
+r5k_sdcache_wbinv_all(void)
+{
+ vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
+ vaddr_t eva = va + mips_sdcache_size;
+
+ while (va < eva) {
+ cache_op_r4k_line(va, R5K_Page_Invalidate_S);
+ va += (128 * 32);
+ }
+}
+
+/* XXX: want wbinv_range_index here instead? */
+void
+r5k_sdcache_wbinv_rangeall(vaddr_t va, vsize_t size)
+{
+ r5k_sdcache_wbinv_all();
+}
+
+#define round_page(x) (((x) + (128 * 32 - 1)) & ~(128 * 32 - 1))
+#define trunc_page(x) ((x) & ~(128 * 32 - 1))
+
+void
+r5k_sdcache_wbinv_range(vaddr_t va, vsize_t size)
+{
+ vaddr_t eva = round_page(va + size);
+ va = trunc_page(va);
+
+ while (va < eva) {
+ cache_op_r4k_line(va, R5K_Page_Invalidate_S);
+ va += (128 * 32);
+ }
+}
+
+void
+r5k_sdcache_wb_range(vaddr_t va, vsize_t size)
+{
+ /* Write-through cache, no need to WB */
+}
diff -r 11388be9bcf3 -r 6e8ec0dc5271 sys/arch/mips/mips/cache_r5k_subr.S
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/mips/cache_r5k_subr.S Sat Mar 08 04:43:24 2003 +0000
@@ -0,0 +1,77 @@
+/* $NetBSD: cache_r5k_subr.S,v 1.1 2003/03/08 04:43:25 rafal Exp $ */
+
+/*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permited provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <mips/asm.h>
+#include <mips/cpuregs.h>
+#include <mips/cache_r4k.h>
+#include <mips/cache_r5k.h>
+
+ .set mips3
+ .set noreorder
+
+/*
+ * r5k_enable_sdcache:
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