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[src/sommerfeld_i386mp_1]: src/sys/arch/i386 Move tlbflushg to cpufunc.h
details: https://anonhg.NetBSD.org/src/rev/9c1fc34dabb8
branches: sommerfeld_i386mp_1
changeset: 482434:9c1fc34dabb8
user: sommerfeld <sommerfeld%NetBSD.org@localhost>
date: Sat Sep 22 23:07:29 2001 +0000
description:
Move tlbflushg to cpufunc.h
diffstat:
sys/arch/i386/i386/pmap.c | 46 +------
sys/arch/i386/include/cpufunc.h | 263 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 264 insertions(+), 45 deletions(-)
diffs (truncated from 327 to 300 lines):
diff -r c9b6d7b27501 -r 9c1fc34dabb8 sys/arch/i386/i386/pmap.c
--- a/sys/arch/i386/i386/pmap.c Sat Sep 22 23:00:54 2001 +0000
+++ b/sys/arch/i386/i386/pmap.c Sat Sep 22 23:07:29 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.83.2.44 2001/09/22 23:01:12 sommerfeld Exp $ */
+/* $NetBSD: pmap.c,v 1.83.2.45 2001/09/22 23:07:29 sommerfeld Exp $ */
/*
*
@@ -3453,50 +3453,6 @@
}
/*
- * XXX belongs in cpufunc.h??
- */
-static __inline void
-tlbflushg(void)
-{
-#if defined(I386_CPU) || defined(I486_CPU) || defined(I586_CPU)
- u_int cr3;
-#endif
-#if defined(I686_CPU)
- u_int ocr4, tcr4;
-#endif
- /*
- * Big hammer: flush all TLB entries from PTE's with the G bit set.
- * This should only be necessary if MP TLB invalidation falls
- * far behind.
- *
- * Intel Architecture Software Developer's Manual, Volume 3,
- * System Programming, section 9.10, "Invalidating the
- * Translation Lookaside Buffers (TLBS)":
- * "The following operations invalidate all TLB entries, irrespective
- * of the setting of the G flag:
- * ...
- * "(P6 family processors only): Writing to control register CR4 to
- * modify the PSE, PGE, or PAE flag."
- *
- * If appropriate, we also reload CR3 for the benefit of
- * pre-P6-family processors.
- */
-
-#if defined(I386_CPU) || defined(I486_CPU) || defined(I586_CPU)
- cr3 = rcr3();
-#endif
-#if defined(I686_CPU)
- ocr4 = rcr4();
- tcr4 = ocr4 & ~CR4_PGE;
- lcr4(tcr4);
- lcr4(ocr4);
-#endif
-#if defined(I386_CPU) || defined(I486_CPU) || defined(I586_CPU)
- lcr3(cr3);
-#endif
-}
-
-/*
* pmap_do_tlb_shootdown:
*
* Process pending TLB shootdown operations for this processor.
diff -r c9b6d7b27501 -r 9c1fc34dabb8 sys/arch/i386/include/cpufunc.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/i386/include/cpufunc.h Sat Sep 22 23:07:29 2001 +0000
@@ -0,0 +1,263 @@
+/* $NetBSD: cpufunc.h,v 1.20.2.2 2001/09/22 23:07:34 sommerfeld Exp $ */
+
+/*-
+ * Copyright (c) 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _I386_CPUFUNC_H_
+#define _I386_CPUFUNC_H_
+
+/*
+ * Functions to provide access to i386-specific instructions.
+ */
+
+#include <sys/cdefs.h>
+#include <sys/types.h>
+
+#include <machine/specialreg.h>
+
+#ifdef _KERNEL
+
+static __inline void
+invlpg(u_int addr)
+{
+ __asm __volatile("invlpg (%0)" : : "r" (addr) : "memory");
+}
+
+static __inline void
+lidt(void *p)
+{
+ __asm __volatile("lidt (%0)" : : "r" (p));
+}
+
+static __inline void
+lldt(u_short sel)
+{
+ __asm __volatile("lldt %0" : : "r" (sel));
+}
+
+static __inline void
+ltr(u_short sel)
+{
+ __asm __volatile("ltr %0" : : "r" (sel));
+}
+
+static __inline void
+lcr0(u_int val)
+{
+ __asm __volatile("movl %0,%%cr0" : : "r" (val));
+}
+
+static __inline u_int
+rcr0(void)
+{
+ u_int val;
+ __asm __volatile("movl %%cr0,%0" : "=r" (val));
+ return val;
+}
+
+static __inline u_int
+rcr2(void)
+{
+ u_int val;
+ __asm __volatile("movl %%cr2,%0" : "=r" (val));
+ return val;
+}
+
+static __inline void
+lcr3(u_int val)
+{
+ __asm __volatile("movl %0,%%cr3" : : "r" (val));
+}
+
+static __inline u_int
+rcr3(void)
+{
+ u_int val;
+ __asm __volatile("movl %%cr3,%0" : "=r" (val));
+ return val;
+}
+
+static __inline void
+lcr4(u_int val)
+{
+ __asm __volatile("movl %0,%%cr4" : : "r" (val));
+}
+
+static __inline u_int
+rcr4(void)
+{
+ u_int val;
+ __asm __volatile("movl %%cr4,%0" : "=r" (val));
+ return val;
+}
+
+static __inline void
+tlbflush(void)
+{
+ u_int val;
+ val = rcr3();
+ lcr3(val);
+}
+
+static __inline void
+tlbflushg(void)
+{
+ /*
+ * Big hammer: flush all TLB entries, including ones from PTE's
+ * with the G bit set. This should only be necessary if TLB
+ * shootdown falls far behind.
+ *
+ * Intel Architecture Software Developer's Manual, Volume 3,
+ * System Programming, section 9.10, "Invalidating the
+ * Translation Lookaside Buffers (TLBS)":
+ * "The following operations invalidate all TLB entries, irrespective
+ * of the setting of the G flag:
+ * ...
+ * "(P6 family processors only): Writing to control register CR4 to
+ * modify the PSE, PGE, or PAE flag."
+ *
+ * (the alternatives not quoted above are not an option here.)
+ *
+ * If PGE is not in use, we reload CR3 for the benefit of
+ * pre-P6-family processors.
+ */
+
+#if defined(I686_CPU)
+ if (cpu_feature & CPUID_PGE) {
+ u_int cr4 = rcr4();
+ lcr4(cr4 & ~CR4_PGE);
+ lcr4(cr4);
+ } else
+#endif
+ tlbflush();
+}
+
+
+#ifdef notyet
+void setidt __P((int idx, /*XXX*/caddr_t func, int typ, int dpl));
+#endif
+
+
+/* XXXX ought to be in psl.h with spl() functions */
+
+static __inline void
+disable_intr(void)
+{
+ __asm __volatile("cli");
+}
+
+static __inline void
+enable_intr(void)
+{
+ __asm __volatile("sti");
+}
+
+static __inline u_long
+read_eflags(void)
+{
+ u_long ef;
+
+ __asm __volatile("pushfl; popl %0" : "=r" (ef));
+ return (ef);
+}
+
+static __inline void
+write_eflags(u_long ef)
+{
+ __asm __volatile("pushl %0; popfl" : : "r" (ef));
+}
+
+static __inline u_int64_t
+rdmsr(u_int msr)
+{
+ u_int64_t rv;
+
+ __asm __volatile("rdmsr" : "=A" (rv) : "c" (msr));
+ return (rv);
+}
+
+static __inline void
+wrmsr(u_int msr, u_int64_t newval)
+{
+ __asm __volatile("wrmsr" : : "A" (newval), "c" (msr));
+}
+
+static __inline void
+wbinvd(void)
+{
+ __asm __volatile("wbinvd");
+}
+
+static __inline u_int64_t
+rdtsc(void)
+{
+ u_int64_t rv;
+
+ __asm __volatile("rdtsc" : "=A" (rv));
+ return (rv);
+}
+
+static __inline u_int64_t
+rdpmc(u_int pmc)
+{
+ u_int64_t rv;
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