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[src/sommerfeld_i386mp_1]: src/sys/arch/i386/include Recent versions of gcc m...
details: https://anonhg.NetBSD.org/src/rev/ed884d8e4e22
branches: sommerfeld_i386mp_1
changeset: 482466:ed884d8e4e22
user: sommerfeld <sommerfeld%NetBSD.org@localhost>
date: Tue Dec 18 02:49:12 2001 +0000
description:
Recent versions of gcc may reorder instructions around inline
functions, breaking the semantics of splraise() and spllower(); to
counteract this, insert a "barrier" (empty asm) as a sequence point.
Reportedly fixes a stability problems on AMD dual-processor systems.
the code-gen barrier primitive will likely move to <sys/cdefs.h> once
we figure out what to call it; in the mean time define it locally.
diffstat:
sys/arch/i386/include/intr.h | 15 ++++++++++++++-
1 files changed, 14 insertions(+), 1 deletions(-)
diffs (43 lines):
diff -r ed933889df52 -r ed884d8e4e22 sys/arch/i386/include/intr.h
--- a/sys/arch/i386/include/intr.h Fri Dec 14 20:32:24 2001 +0000
+++ b/sys/arch/i386/include/intr.h Tue Dec 18 02:49:12 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.12.10.16 2001/07/19 08:57:30 sommerfeld Exp $ */
+/* $NetBSD: intr.h,v 1.12.10.17 2001/12/18 02:49:12 sommerfeld Exp $ */
/*-
* Copyright (c) 1998, 2001 The NetBSD Foundation, Inc.
@@ -101,6 +101,17 @@
static __inline void softintr __P((int));
/*
+ * compiler barrier: prevent reordering of instructions.
+ * XXX something similar will move to <sys/cdefs.h>
+ * or thereabouts.
+ * This prevents the compiler from reordering code around
+ * this "instruction", acting as a sequence point for code generation.
+ */
+
+#define __splbarrier() __asm __volatile("":::"memory")
+
+
+/*
* Add a mask to cpl, and return the old value of cpl.
*/
static __inline int
@@ -111,6 +122,7 @@
if (ncpl > ocpl)
lapic_tpr = ncpl;
+ __splbarrier();
return (ocpl);
}
@@ -124,6 +136,7 @@
{
register int cmask;
+ __splbarrier();
lapic_tpr = ncpl;
cmask = IUNMASK(ncpl);
if (ipending & cmask)
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