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[src/trunk]: src/sys/arch/sparc64 Allow multiple 4MB pages for both kernel te...
details: https://anonhg.NetBSD.org/src/rev/f279cce396d9
branches: trunk
changeset: 511521:f279cce396d9
user: eeh <eeh%NetBSD.org@localhost>
date: Thu Jun 21 00:24:22 2001 +0000
description:
Allow multiple 4MB pages for both kernel text and kernel data.
Note: DEBUG checks will not allow accesses to the hole between
text and data segments, so you may need to update programs that
use libkvm before relocating the start of kernel data.
diffstat:
sys/arch/sparc64/include/pte.h | 29 ++-
sys/arch/sparc64/sparc64/locore.s | 348 +++++++++++++++++++++----------------
sys/arch/sparc64/sparc64/pmap.c | 245 ++++++++++++++++----------
3 files changed, 370 insertions(+), 252 deletions(-)
diffs (truncated from 1092 to 300 lines):
diff -r fbc9c3b6716d -r f279cce396d9 sys/arch/sparc64/include/pte.h
--- a/sys/arch/sparc64/include/pte.h Thu Jun 21 00:10:49 2001 +0000
+++ b/sys/arch/sparc64/include/pte.h Thu Jun 21 00:24:22 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pte.h,v 1.5 1999/06/05 21:58:18 eeh Exp $ */
+/* $NetBSD: pte.h,v 1.6 2001/06/21 00:24:22 eeh Exp $ */
/*
* Copyright (c) 1996-1999 Eduardo Horvath
@@ -127,12 +127,29 @@
#define TSB_TAG_VA(t) ((((int64_t)(t))<<TSB_TAG_VA_SHIFT))
#define TSB_TAG(g,ctx,va) ((((u_int64_t)((g)!=0))<<63)|(((u_int64_t)(ctx)&CTX_MASK)<<TSB_TAG_CTX_SHIFT)|(((u_int64_t)va)>>TSB_TAG_VA_SHIFT))
+/* Page sizes */
+#define PGSZ_8K 0
+#define PGSZ_64K 1
+#define PGSZ_512K 2
+#define PGSZ_4M 3
+
+#define PGSZ_SHIFT 61
+
+/*
+ * Why couldn't Sun pick better page sizes?
+ *
+ * Page sizes are 2**(12+(3*sz)), except for 8K which
+ * is 2**12+1 instead of 2**12.
+ */
+#define PG_SZ(s) (1<<(12+(s?(3*s):1)))
+#define TLB_SZ(s) (((uint64_t)(s))<<PGSZ_SHIFT)
+
/* TLB data masks */
#define TLB_V 0x8000000000000000LL
-#define TLB_8K 0x0000000000000000LL
-#define TLB_64K 0x2000000000000000LL
-#define TLB_512K 0x4000000000000000LL
-#define TLB_4M 0x6000000000000000LL
+#define TLB_8K TLB_SZ(PGSZ_8K)
+#define TLB_64K TLB_SZ(PGSZ_64K)
+#define TLB_512K TLB_SZ(PGSZ_512K)
+#define TLB_4M TLB_SZ(PGSZ_4M)
#define TLB_SZ_MASK 0x6000000000000000LL
#define TLB_NFO 0x1000000000000000LL
#define TLB_IE 0x0800000000000000LL
@@ -192,7 +209,7 @@
"b\3E\0" "b\2P\0" "b\1W\0" "b\0G\0"
#define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie) \
-(((valid)?TLB_V:0LL)|(sz)|(((u_int64_t)(pa))&TLB_PA_MASK)|\
+(((valid)?TLB_V:0LL)|TLB_SZ(sz)|(((u_int64_t)(pa))&TLB_PA_MASK)|\
((cache)?((aliased)?TLB_CP:TLB_CACHE_MASK):TLB_E)|\
((priv)?TLB_P:0LL)|((write)?TLB_W:0LL)|((g)?TLB_G:0LL)|((ie)?TLB_IE:0LL))
diff -r fbc9c3b6716d -r f279cce396d9 sys/arch/sparc64/sparc64/locore.s
--- a/sys/arch/sparc64/sparc64/locore.s Thu Jun 21 00:10:49 2001 +0000
+++ b/sys/arch/sparc64/sparc64/locore.s Thu Jun 21 00:24:22 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.117 2001/06/06 21:19:49 mrg Exp $ */
+/* $NetBSD: locore.s,v 1.118 2001/06/21 00:24:22 eeh Exp $ */
/*
* Copyright (c) 1996-2000 Eduardo Horvath
@@ -75,7 +75,6 @@
#undef SCHED_DEBUG
#include "opt_ddb.h"
-#include "opt_kgdb.h"
#include "opt_multiprocessor.h"
#include "opt_lockdebug.h"
@@ -5488,6 +5487,8 @@
/*
* Step 4: compute number of windows and set up tables.
* We could do some of this later.
+ *
+ * XXX I forget: why are we doing this?
*/
rdpr %ver, %g1
and %g1, 0x0f, %g1 ! want just the CWP bits
@@ -5544,16 +5545,15 @@
*
* Register usage in this section:
*
- * %l0 = KERNBASE
- * %l1 = TLB Data w/o low bits
- * %l2 = TLB Data w/low bits
- * %l3 = tmp
- * %l4 = tmp
- * %l5 = tmp && TLB_TAG_ACCESS
- * %l6 = tmp && CTX_PRIMARY
- * %l7 = DATA_START
- * %g1 = TLB Data for data segment w/o low bits
- * %g2 = TLB Data for data segment w/low bits
+ * %l0 = ktext (also KERNBASE)
+ * %l1 = ektext
+ * %l2 = ktextp/TTE Data for text w/o low bits
+ * %l3 = kdata (also DATA_START)
+ * %l4 = ekdata
+ * %l5 = kdatap/TTE Data for data w/o low bits
+ * %l6 = 4MB
+ * %l7 = 4MB-1
+ * %o0-%o5 = tmp
*/
#ifdef NO_VCACHE
@@ -5566,68 +5566,78 @@
wrpr %g0, 0, %tl ! Make sure we're not in NUCLEUS mode
sethi %hi(KERNBASE), %l0 ! Find our xlation
- sethi %hi(DATA_START), %l7
-
- set _C_LABEL(ktextp), %l1 ! Find phys addr
- ldx [%l1], %l1 ! The following gets ugly: We need to load the following mask
- set _C_LABEL(kdatap), %g1
- ldx [%g1], %g1
-
- sethi %hi(0xe0000000), %l2 ! V=1|SZ=11|NFO=0|IE=0
- sllx %l2, 32, %l2 ! Shift it into place
-
- mov -1, %l3 ! Create a nice mask
- sllx %l3, 41, %l4 ! Mask off high bits
- or %l4, 0xfff, %l4 ! We can just load this in 12 (of 13) bits
-
- andn %l1, %l4, %l1 ! Mask the phys page number
- andn %g1, %l4, %g1 ! Mask the phys page number
-
- or %l2, %l1, %l1 ! Now take care of the high bits
- or %l2, %g1, %g1 ! Now take care of the high bits
-! or %l1, 0x076, %l1 ! And low bits: L=1|CP=1|CV=1|E=0|P=1|W=0|G=0
-! or %g1, 0x076, %g2 ! And low bits: L=1|CP=1|CV=1|E=0|P=1|W=1(ugh)|G=0
+ sethi %hi(DATA_START), %l3
+
+ set _C_LABEL(ktextp), %l2 ! Find phys addr
+ ldx [%l2], %l2 ! The following gets ugly: We need to load the following mask
+ set _C_LABEL(kdatap), %l5
+ ldx [%l5], %l5
+
+ set _C_LABEL(ektext), %l1 ! And the ends...
+ ldx [%l1], %l1
+ set _C_LABEL(ekdata), %l4
+ ldx [%l4], %l4
+
+ sethi %hi(0xe0000000), %o0 ! V=1|SZ=11|NFO=0|IE=0
+ sllx %o0, 32, %o0 ! Shift it into place
+
+ sethi %hi(0x400000), %l6 ! Create a 4MB mask
+ add %l6, -1, %l7
+
+ mov -1, %o1 ! Create a nice mask
+ sllx %o1, 41, %o1 ! Mask off high bits
+ or %o1, 0xfff, %o1 ! We can just load this in 12 (of 13) bits
+
+ andn %l2, %o1, %l2 ! Mask the phys page number
+ andn %l5, %o1, %l5 ! Mask the phys page number
+
+ or %l2, %o0, %l2 ! Now take care of the high bits
+ or %l5, %o0, %l5 ! Now take care of the high bits
wrpr %g0, PSTATE_KERN, %pstate ! Disable interrupts
-! call print_dtlb ! Debug printf
-! nop ! delay
#ifdef DEBUG
set 1f, %o0 ! Debug printf for TEXT page
srlx %l0, 32, %o1
srl %l0, 0, %o2
- or %l1, TTE_L|TTE_CP|TTE_CV|TTE_P|TTE_W, %l2 ! And low bits: L=1|CP=1|CV=1|E=0|P=1|W=1(ugh)|G=0
- srlx %l2, 32, %o3
+ or %l2, TTE_L|TTE_CP|TTE_CV|TTE_P, %o4 ! And low bits: L=1|CP=1|CV=1|E=0|P=1|W=1(ugh)|G=0
+ srlx %o4, 32, %o3
call _C_LABEL(prom_printf)
- srl %l2, 0, %o4
+ srl %o4, 0, %o4
set 1f, %o0 ! Debug printf for DATA page
- srlx %l7, 32, %o1
- srl %l7, 0, %o2
- or %g1, TTE_L|TTE_CP|TTE_CV|TTE_P|TTE_W, %l2 ! And low bits: L=1|CP=1|CV=1|E=0|P=1|W=1(ugh)|G=0
- srlx %l2, 32, %o3
+ srlx %l3, 32, %o1
+ srl %l3, 0, %o2
+ or %l5, TTE_L|TTE_CP|TTE_CV|TTE_P|TTE_W, %o4 ! And low bits: L=1|CP=1|CV=1|E=0|P=1|W=1(ugh)|G=0
+ srlx %o4, 32, %o3
call _C_LABEL(prom_printf)
- srl %l2, 0, %o4
+ srl %o4, 0, %o4
.data
1:
.asciz "Setting DTLB entry %08x %08x data %08x %08x\r\n"
_ALIGN
.text
#endif
- set 0x400000, %l3 ! Demap all of kernel dmmu text segment
- mov %l0, %l5
- mov %l7, %l6
- set 0x2000, %l4 ! 8K page size
- add %l0, %l3, %l3
+ mov %l0, %o0 ! Demap all of kernel dmmu text segment
+ mov %l3, %o1
+ set 0x2000, %o2 ! 8K page size
+ add %l1, %l7, %o5 ! Extend to 4MB boundary
+ andn %o5, %l7, %o5
0:
- stxa %l6, [%l6] ASI_DMMU_DEMAP
- add %l6, %l4, %l6
+ stxa %o0, [%o0] ASI_DMMU_DEMAP ! Demap text segment
membar #Sync
- stxa %l5, [%l5] ASI_DMMU_DEMAP ! Demap it
+ cmp %o0, %o5
+ bleu 0b
+ add %o0, %o2, %o0
+
+ add %l4, %l7, %o5 ! Extend to 4MB boundary
+ andn %o5, %l7, %o5
+0:
+ stxa %o1, [%o1] ASI_DMMU_DEMAP ! Demap data segment
membar #Sync
- cmp %l5, %l3
+ cmp %o1, %o5
bleu 0b
- add %l5, %l4, %l5
+ add %o1, %o2, %o1
set (1<<14)-8, %o0 ! Clear out DCACHE
1:
@@ -5636,47 +5646,67 @@
brnz,pt %o0, 1b
dec 8, %o0
- set TLB_TAG_ACCESS, %l5 ! Now map it back in with a locked TTE
+ /*
+ * First map data segment into the DMMU.
+ */
+ set TLB_TAG_ACCESS, %o0 ! Now map it back in with a locked TTE
+ mov %l3, %o1
#ifdef NO_VCACHE
- ! And low bits: L=1|CP=1|CV=0(ugh)|E=0|P=1|W=0|G=0
- or %l1, TTE_L|TTE_CP|TTE_P, %l2
+ ! And low bits: L=1|CP=1|CV=0(ugh)|E=0|P=1|W=1|G=0
+ or %l5, TTE_L|TTE_CP|TTE_P|TTE_W, %o2
#else
- ! And low bits: L=1|CP=1|CV=1|E=0|P=1|W=0|G=0
- or %l1, TTE_L|TTE_CP|TTE_CV|TTE_P, %l2
+ ! And low bits: L=1|CP=1|CV=1|E=0|P=1|W=1|G=0
+ or %l5, TTE_L|TTE_CP|TTE_CV|TTE_P|TTE_W, %o2
#endif
set 1f, %o5
- stxa %l0, [%l5] ASI_DMMU ! Same for DMMU
+2:
+ stxa %o1, [%o0] ASI_DMMU ! Set VA for DSEG
membar #Sync ! We may need more membar #Sync in here
- stxa %l2, [%g0] ASI_DMMU_DATA_IN ! Same for DMMU
+ stxa %o2, [%g0] ASI_DMMU_DATA_IN ! Store TTE for DSEG
membar #Sync ! We may need more membar #Sync in here
flush %o5 ! Make IMMU see this too
+1:
+ add %o1, %l6, %o1 ! increment VA
+ cmp %o1, %l4 ! Next 4MB mapping....
+ blu,pt %xcc, 2b
+ add %o2, %l6, %o2 ! Increment tag
+
+ /*
+ * Next map the text segment into the DMMU so we can get at RODATA.
+ */
+ mov %l0, %o1
#ifdef NO_VCACHE
- ! And low bits: L=1|CP=1|CV=0(ugh)|E=0|P=1|W=1|G=0
- or %g1, TTE_L|TTE_CP|TTE_P|TTE_W, %l2
+ ! And low bits: L=1|CP=1|CV=0(ugh)|E=0|P=1|W=0|G=0
+ or %l2, TTE_L|TTE_CP|TTE_P, %o2
#else
- ! And low bits: L=1|CP=1|CV=1|E=0|P=1|W=1|G=0
- or %g1, TTE_L|TTE_CP|TTE_CV|TTE_P|TTE_W, %l2
-#endif
- stxa %l7, [%l5] ASI_DMMU ! Same for DMMU
+ ! And low bits: L=1|CP=1|CV=1|E=0|P=1|W=0|G=0
+ or %l2, TTE_L|TTE_CP|TTE_CV|TTE_P, %o2
+#endif
+2:
+ stxa %o1, [%o0] ASI_DMMU ! Set VA for DSEG
membar #Sync ! We may need more membar #Sync in here
- stxa %l2, [%g0] ASI_DMMU_DATA_IN ! Same for DMMU
+ stxa %o2, [%g0] ASI_DMMU_DATA_IN ! Store TTE for DSEG
membar #Sync ! We may need more membar #Sync in here
flush %o5 ! Make IMMU see this too
-1:
+ add %o1, %l6, %o1 ! increment VA
+ cmp %o1, %l1 ! Next 4MB mapping....
+ blu,pt %xcc, 2b
+ add %o2, %l6, %o2 ! Increment tag
+
#ifdef DEBUG
set 1f, %o0 ! Debug printf
srlx %l0, 32, %o1
srl %l0, 0, %o2
- srlx %l2, 32, %o3
+ or %l2, TTE_L|TTE_CP|TTE_CV|TTE_P, %o4
+ srlx %o4, 32, %o3
call _C_LABEL(prom_printf)
- srl %l2, 0, %o4
+ srl %o4, 0, %o4
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