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[src/sommerfeld_i386mp_1]: src/sys/arch/i386/include Add Athlon performance c...
details: https://anonhg.NetBSD.org/src/rev/fb2e562e7f83
branches: sommerfeld_i386mp_1
changeset: 482541:fb2e562e7f83
user: gmcgarry <gmcgarry%NetBSD.org@localhost>
date: Fri Jun 07 04:03:50 2002 +0000
description:
Add Athlon performance counters.
diffstat:
sys/arch/i386/include/specialreg.h | 553 +++++++++++++++++++++++++++++++++++++
1 files changed, 553 insertions(+), 0 deletions(-)
diffs (truncated from 557 to 300 lines):
diff -r d05806c9b4a1 -r fb2e562e7f83 sys/arch/i386/include/specialreg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/i386/include/specialreg.h Fri Jun 07 04:03:50 2002 +0000
@@ -0,0 +1,553 @@
+/* $NetBSD: specialreg.h,v 1.23.2.2 2002/06/07 04:03:50 gmcgarry Exp $ */
+
+/*-
+ * Copyright (c) 1991 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)specialreg.h 7.1 (Berkeley) 5/9/91
+ */
+
+/*
+ * Bits in 386 special registers:
+ */
+#define CR0_PE 0x00000001 /* Protected mode Enable */
+#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
+#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
+#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
+#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
+#define CR0_PG 0x80000000 /* PaGing enable */
+
+/*
+ * Bits in 486 special registers:
+ */
+#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
+#define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */
+#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
+#define CR0_NW 0x20000000 /* Not Write-through */
+#define CR0_CD 0x40000000 /* Cache Disable */
+
+/*
+ * Cyrix 486 DLC special registers, accessible as IO ports.
+ */
+#define CCR0 0xc0 /* configuration control register 0 */
+#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */
+#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
+#define CCR0_A20M 0x04 /* enables A20M# input pin */
+#define CCR0_KEN 0x08 /* enables KEN# input pin */
+#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */
+#define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */
+#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */
+#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */
+
+#define CCR1 0xc1 /* configuration control register 1 */
+#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */
+/* the remaining 7 bits of this register are reserved */
+
+/*
+ * bits in the pentiums %cr4 register:
+ */
+
+#define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */
+#define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */
+#define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */
+#define CR4_DE 0x00000008 /* debugging extension */
+#define CR4_PSE 0x00000010 /* large (4MB) page size enable */
+#define CR4_PAE 0x00000020 /* physical address extension enable */
+#define CR4_MCE 0x00000040 /* machine check enable */
+#define CR4_PGE 0x00000080 /* page global enable */
+#define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */
+#define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */
+#define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
+
+/*
+ * CPUID "features" bits:
+ */
+
+#define CPUID_FPU 0x00000001 /* processor has an FPU? */
+#define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
+#define CPUID_DE 0x00000004 /* has debugging extension */
+#define CPUID_PSE 0x00000008 /* has page 4MB page size extension */
+#define CPUID_TSC 0x00000010 /* has time stamp counter */
+#define CPUID_MSR 0x00000020 /* has mode specific registers */
+#define CPUID_PAE 0x00000040 /* has phys address extension */
+#define CPUID_MCE 0x00000080 /* has machine check exception */
+#define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
+#define CPUID_APIC 0x00000200 /* has enabled APIC */
+#define CPUID_B10 0x00000400 /* reserved, MTRR */
+#define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */
+#define CPUID_MTRR 0x00001000 /* has memory type range register */
+#define CPUID_PGE 0x00002000 /* has page global extension */
+#define CPUID_MCA 0x00004000 /* has machine check architecture */
+#define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
+#define CPUID_FGPAT 0x00010000 /* Page Attribute Table */
+#define CPUID_PSE36 0x00020000 /* 36-bit PSE */
+#define CPUID_PN 0x00040000 /* processor serial number */
+#define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
+#define CPUID_B20 0x00100000 /* reserved */
+#define CPUID_DS 0x00200000 /* Debug Store */
+#define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
+#define CPUID_MMX 0x00800000 /* MMX supported */
+#define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */
+#define CPUID_SSE 0x02000000 /* streaming SIMD extensions */
+#define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */
+#define CPUID_SS 0x08000000 /* self-snoop */
+#define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */
+#define CPUID_TM 0x20000000 /* thermal monitor (TCC) */
+#define CPUID_B30 0x40000000 /* reserved */
+#define CPUID_B31 0x80000000 /* reserved */
+
+#define CPUID_FLAGS1 "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE" \
+ "\10MCE\11CX8\12APIC\13B10\14SEP\15MTRR"
+#define CPUID_MASK1 0x00001fff
+#define CPUID_FLAGS2 "\20\16PGE\17MCA\20CMOV\21FGPAT\22PSE36\23PN\24CFLUSH" \
+ "\25B20\26DS\27ACPI\30MMX"
+#define CPUID_MASK2 0x00ffe000
+#define CPUID_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM\37B30\40B31"
+#define CPUID_MASK3 0xff000000
+
+/*
+ * Model-specific registers for the i386 family
+ */
+#define MSR_P5_MC_ADDR 0x000 /* P5 only */
+#define MSR_P5_MC_TYPE 0x001 /* P5 only */
+#define MSR_TSC 0x010
+#define MSR_CESR 0x011 /* P5 only (trap on P6) */
+#define MSR_CTR0 0x012 /* P5 only (trap on P6) */
+#define MSR_CTR1 0x013 /* P5 only (trap on P6) */
+#define MSR_APICBASE 0x01b
+#define MSR_EBL_CR_POWERON 0x02a
+#define MSR_TEST_CTL 0x033
+#define MSR_BIOS_UPDT_TRIG 0x079
+#define MSR_BBL_CR_D0 0x088 /* PII+ only */
+#define MSR_BBL_CR_D1 0x089 /* PII+ only */
+#define MSR_BBL_CR_D2 0x08a /* PII+ only */
+#define MSR_BIOS_SIGN 0x08b
+#define MSR_PERFCTR0 0x0c1
+#define MSR_PERFCTR1 0x0c2
+#define MSR_MTRRcap 0x0fe
+#define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
+#define MSR_BBL_CR_DECC 0x118 /* PII+ only */
+#define MSR_BBL_CR_CTL 0x119 /* PII+ only */
+#define MSR_BBL_CR_TRIG 0x11a /* PII+ only */
+#define MSR_BBL_CR_BUSY 0x11b /* PII+ only */
+#define MSR_BBL_CR_CTR3 0x11e /* PII+ only */
+#define MSR_MCG_CAP 0x179
+#define MSR_MCG_STATUS 0x17a
+#define MSR_MCG_CTL 0x17b
+#define MSR_EVNTSEL0 0x186
+#define MSR_EVNTSEL1 0x187
+#define MSR_DEBUGCTLMSR 0x1d9
+#define MSR_LASTBRANCHFROMIP 0x1db
+#define MSR_LASTBRANCHTOIP 0x1dc
+#define MSR_LASTINTFROMIP 0x1dd
+#define MSR_LASTINTTOIP 0x1de
+#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
+#define MSR_MTRRphysBase0 0x200
+#define MSR_MTRRphysMask0 0x201
+#define MSR_MTRRphysBase1 0x202
+#define MSR_MTRRphysMask1 0x203
+#define MSR_MTRRphysBase2 0x204
+#define MSR_MTRRphysMask2 0x205
+#define MSR_MTRRphysBase3 0x206
+#define MSR_MTRRphysMask3 0x207
+#define MSR_MTRRphysBase4 0x208
+#define MSR_MTRRphysMask4 0x209
+#define MSR_MTRRphysBase5 0x20a
+#define MSR_MTRRphysMask5 0x20b
+#define MSR_MTRRphysBase6 0x20c
+#define MSR_MTRRphysMask6 0x20d
+#define MSR_MTRRphysBase7 0x20e
+#define MSR_MTRRphysMask7 0x20f
+#define MSR_MTRRfix64K_00000 0x250
+#define MSR_MTRRfix16K_80000 0x258
+#define MSR_MTRRfix16K_A0000 0x259
+#define MSR_MTRRfix4K_C0000 0x268
+#define MSR_MTRRfix4K_C8000 0x269
+#define MSR_MTRRfix4K_D0000 0x26a
+#define MSR_MTRRfix4K_D8000 0x26b
+#define MSR_MTRRfix4K_E0000 0x26c
+#define MSR_MTRRfix4K_E8000 0x26d
+#define MSR_MTRRfix4K_F0000 0x26e
+#define MSR_MTRRfix4K_F8000 0x26f
+#define MSR_MTRRdefType 0x2ff
+#define MSR_MC0_CTL 0x400
+#define MSR_MC0_STATUS 0x401
+#define MSR_MC0_ADDR 0x402
+#define MSR_MC0_MISC 0x403
+#define MSR_MC1_CTL 0x404
+#define MSR_MC1_STATUS 0x405
+#define MSR_MC1_ADDR 0x406
+#define MSR_MC1_MISC 0x407
+#define MSR_MC2_CTL 0x408
+#define MSR_MC2_STATUS 0x409
+#define MSR_MC2_ADDR 0x40a
+#define MSR_MC2_MISC 0x40b
+#define MSR_MC4_CTL 0x40c
+#define MSR_MC4_STATUS 0x40d
+#define MSR_MC4_ADDR 0x40e
+#define MSR_MC4_MISC 0x40f
+#define MSR_MC3_CTL 0x410
+#define MSR_MC3_STATUS 0x411
+#define MSR_MC3_ADDR 0x412
+#define MSR_MC3_MISC 0x413
+
+/*
+ * AMD K6/K7 MSRs.
+ */
+#define MSR_K6_UWCCR 0xc0000085
+#define MSR_K7_EVNTSEL0 0xc0010000
+#define MSR_K7_EVNTSEL1 0xc0010001
+#define MSR_K7_EVNTSEL2 0xc0010002
+#define MSR_K7_EVNTSEL3 0xc0010003
+#define MSR_K7_PERFCTR0 0xc0010004
+#define MSR_K7_PERFCTR1 0xc0010005
+#define MSR_K7_PERFCTR2 0xc0010006
+#define MSR_K7_PERFCTR3 0xc0010007
+
+/*
+ * Constants related to MTRRs
+ */
+#define MTRR_N64K 8 /* numbers of fixed-size entries */
+#define MTRR_N16K 16
+#define MTRR_N4K 64
+
+/*
+ * the following four 3-byte registers control the non-cacheable regions.
+ * These registers must be written as three separate bytes.
+ *
+ * NCRx+0: A31-A24 of starting address
+ * NCRx+1: A23-A16 of starting address
+ * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
+ *
+ * The non-cacheable region's starting address must be aligned to the
+ * size indicated by the NCR_SIZE_xx field.
+ */
+#define NCR1 0xc4
+#define NCR2 0xc7
+#define NCR3 0xca
+#define NCR4 0xcd
+
+#define NCR_SIZE_0K 0
+#define NCR_SIZE_4K 1
+#define NCR_SIZE_8K 2
+#define NCR_SIZE_16K 3
+#define NCR_SIZE_32K 4
+#define NCR_SIZE_64K 5
+#define NCR_SIZE_128K 6
+#define NCR_SIZE_256K 7
+#define NCR_SIZE_512K 8
+#define NCR_SIZE_1M 9
+#define NCR_SIZE_2M 10
+#define NCR_SIZE_4M 11
+#define NCR_SIZE_8M 12
+#define NCR_SIZE_16M 13
+#define NCR_SIZE_32M 14
+#define NCR_SIZE_4G 15
+
+/*
+ * Performance monitor events.
+ *
+ * Note that 586-class and 686-class CPUs have different performance
+ * monitors available, and they are accessed differently:
+ *
+ * 686-class: `rdpmc' instruction
+ * 586-class: `rdmsr' instruction, CESR MSR
+ *
+ * The descriptions of these events are too lenghy to include here.
+ * See Appendix A of "Intel Architecture Software Developer's
+ * Manual, Volume 3: System Programming" for more information.
+ */
+
+/*
+ * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits
+ * is CTR1.
+ */
+
+#define PMC5_CESR_EVENT 0x003f
+#define PMC5_CESR_OS 0x0040
+#define PMC5_CESR_USR 0x0080
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