[src/sommerfeld_i386mp_1]: src/sys/arch/i386/i386 add some minor instrumentat...

[sommerfeld <sommerfeld%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/a9ec3da8d227
branches:  sommerfeld_i386mp_1
changeset: 482308:a9ec3da8d227
user:      sommerfeld <sommerfeld%NetBSD.org@localhost>
date:      Sat Nov 18 22:48:10 2000 +0000

description:
add some minor instrumentation framework.
cache-line align shootdown job pool entries.
rewrite tlbflushg to use the {r,l}cr{3,4}; minimise the pain based on
which CPU we support..

diffstat:

 sys/arch/i386/i386/pmap.c |  45 ++++++++++++++++++++++++++++++---------------
 1 files changed, 30 insertions(+), 15 deletions(-)

diffs (137 lines):

diff -r 4bf9844f23cc -r a9ec3da8d227 sys/arch/i386/i386/pmap.c
--- a/sys/arch/i386/i386/pmap.c Thu Nov 02 01:02:08 2000 +0000
+++ b/sys/arch/i386/i386/pmap.c Sat Nov 18 22:48:10 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.83.2.11 2000/09/06 03:28:36 sommerfeld Exp $        */
+/*     $NetBSD: pmap.c,v 1.83.2.12 2000/11/18 22:48:10 sommerfeld Exp $        */
 
 /*
  *
@@ -266,6 +266,8 @@
 
 #endif
 
+#define COUNT(x)       /* nothing */
+
 #ifndef I386_MAXPROCS
 #define I386_MAXPROCS 0
 #define cpu_number() 0
@@ -635,6 +637,7 @@
        }
 
        /* need to load a new alternate pt space into curpmap? */
+       COUNT(apdp_pde_map);
        opde = *APDP_PDE;
        if (!pmap_valid_entry(opde) || (opde & PG_FRAME) != pmap->pm_pdirpa) {
                *APDP_PDE = (pd_entry_t) (pmap->pm_pdirpa | PG_RW | PG_V);
@@ -665,6 +668,7 @@
                pmap_update();
                /* XXX MP need floosh here? */
 #endif
+               COUNT(apdp_pde_unmap);
                simple_unlock(&pmap->pm_obj.vmobjlock);
                simple_unlock(&curpcb->pcb_pmap->pm_obj.vmobjlock);
        }
@@ -1044,7 +1048,7 @@
 
        pool_init(&pmap_tlb_shootdown_job_pool,
            sizeof(struct pmap_tlb_shootdown_job),
-           0,                  /* align.  XXX cache-line align these?? */
+           32,                 /* cache-line align XXX magic number*/
            0,                  /* ioff */
            PR_STATIC,
            "pmaptlbpl",
@@ -1393,6 +1397,7 @@
            !simple_lock_try(&cpv->pv_pmap->pm_obj.vmobjlock))
                return(FALSE);
 
+       COUNT(try_steal_pv);
        /*
         * yes, we can try and steal it.   first we need to remove the
         * mapping from the pmap.
@@ -1816,6 +1821,7 @@
 #ifdef MULTIPROCESSOR
                                /* XXX XXX MP */
                                /* BARF */
+                               printf("pmap: stealing PTP!\n");
 #endif
                                
                                if (pmap_is_curpmap(pmaps_hand))
@@ -2335,8 +2341,6 @@
  * worthy of flushing.  If we don't have space to save it, either flush
  * it immediately (for global mappings), or mark the prr so we do a
  * complete TLB flush when done.
- *
- * XXX this could probably be trivially merged with the TLB flush pool.
  */
 
 __inline static void
@@ -4041,7 +4045,7 @@
                }
                if (count == 0)
                        break;
-               DELAY(10);      /* XXX MP safe? */
+               DELAY(10);
        }
        printf("escaped after %d spins\n", spincount);
        
@@ -4140,8 +4144,12 @@
 static __inline void
 tlbflushg(void)
 {
-       u_int cr3, ocr4, tcr4;
-       
+#if defined(I386_CPU) || defined(I486_CPU) || defined(I586_CPU)
+       u_int cr3;
+#endif
+#if defined(I686_CPU)
+       u_int ocr4, tcr4;
+#endif
        /*
         * Big hammer: flush all TLB entries from PTE's with the G bit set.
         * This should only be necessary if MP TLB invalidation falls
@@ -4156,17 +4164,22 @@
         * "(P6 family processors only): Writing to control register CR4 to
         * modify the PSE, PGE, or PAE flag."
         *
-        * The following is coded defensively, and is probably mega-overkill.
-        * We also reload CR3 for the benefit of pre-P6-family processors.
+        * If appropriate, we also reload CR3 for the benefit of
+        * pre-P6-family processors.
         */
         
-       __asm __volatile("movl %%cr3,%0" : "=r" (cr3));
-       __asm __volatile("movl %%cr4,%0" : "=r" (ocr4));
+#if defined(I386_CPU) || defined(I486_CPU) || defined(I586_CPU)
+       cr3 = rcr3();
+#endif
+#if defined(I686_CPU)
+       ocr4 = rcr4();
        tcr4 = ocr4 & ~CR4_PGE;
-       __asm __volatile("movl %0,%%cr4" : "=r" (tcr4));        
-       __asm __volatile("movl %0,%%cr3" : : "r" (cr3)); /* is this needed? */
-       __asm __volatile("movl %0,%%cr4" : "=r" (ocr4));
-       __asm __volatile("movl %0,%%cr3" : : "r" (cr3));
+       lcr4(tcr4);
+       lcr4(ocr4);
+#endif
+#if defined(I386_CPU) || defined(I486_CPU) || defined(I586_CPU)
+       lcr3(cr3);
+#endif
 }
 
 
@@ -4217,11 +4230,13 @@
        simple_lock(&pq->pq_slock);
        
        if (pq->pq_flushg) {
+               COUNT(flushg);
                tlbflushg();
                pq->pq_flushg = 0;
                pq->pq_flushu = 0;
                pmap_tlb_shootdown_q_drain(pq);
        } else if (pq->pq_flushu) {
+               COUNT(flushu);
                tlbflush();
                pq->pq_flushu = 0;
                pmap_tlb_shootdown_q_drain(pq);