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[src/sommerfeld_i386mp_1]: src/sys/arch/i386/mca Fix so these files build wit...



details:   https://anonhg.NetBSD.org/src/rev/e616aabc50f6
branches:  sommerfeld_i386mp_1
changeset: 482454:e616aabc50f6
user:      sommerfeld <sommerfeld%NetBSD.org@localhost>
date:      Tue Dec 04 20:00:17 2001 +0000

description:
Fix so these files build with options DEBUG enabled.
The change to edc_mca.c may not work as I don't have any mca hardware.

diffstat:

 sys/arch/i386/mca/mca_machdep.c |  593 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 593 insertions(+), 0 deletions(-)

diffs (truncated from 597 to 300 lines):

diff -r 6d9a42932c1a -r e616aabc50f6 sys/arch/i386/mca/mca_machdep.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/i386/mca/mca_machdep.c   Tue Dec 04 20:00:17 2001 +0000
@@ -0,0 +1,593 @@
+/*     $NetBSD: mca_machdep.c,v 1.14.2.2 2001/12/04 20:00:17 sommerfeld Exp $  */
+
+/*-
+ * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
+ * Copyright (c) 1996-1999 Scott D. Telford.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Scott Telford <s.telford%ed.ac.uk@localhost> and Jaromir Dolecek
+ * <jdolecek%NetBSD.org@localhost>.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *     This product includes software developed by the NetBSD
+ *     Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Machine-specific functions for MCA autoconfiguration.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mca_machdep.c,v 1.14.2.2 2001/12/04 20:00:17 sommerfeld Exp $");
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/systm.h>
+#include <sys/syslog.h>
+#include <sys/time.h>
+#include <sys/kernel.h>
+
+#include <machine/bioscall.h>
+#include <machine/psl.h>
+
+#define _I386_BUS_DMA_PRIVATE
+#include <machine/bus.h>
+
+#include <i386/isa/icu.h>
+#include <dev/isa/isavar.h>
+#include <dev/isa/isareg.h>
+#include <dev/mca/mcavar.h>
+#include <dev/mca/mcareg.h>
+
+#include "isa.h"
+#include "opt_mcaverbose.h"
+
+/* System Configuration Block - this info is returned by the BIOS call */
+struct bios_config {
+       u_int16_t       count;
+       u_int8_t        model;
+       u_int8_t        submodel;
+       u_int8_t        bios_rev;
+       u_int8_t        feature1;
+#define FEATURE_MCAISA 0x01    /* Machine contains both MCA and ISA bus */
+#define FEATURE_MCABUS 0x02    /* Machine has MCA bus instead of ISA   */
+#define FEATURE_EBDA   0x04    /* Extended BIOS data area allocated    */
+#define FEATURE_WAITEV 0x08    /* Wait for external event is supported */
+#define FEATURE_KBDINT 0x10    /* Keyboard intercept called by Int 09h */
+#define FEATURE_RTC    0x20    /* Real-time clock present              */
+#define FEATURE_IC2    0x40    /* Second interrupt chip present        */
+#define FEATURE_DMA3   0x80    /* DMA channel 3 used by hard disk BIOS */
+       u_int8_t        feature2;
+       u_int8_t        pad[9];
+} __attribute__ ((packed));
+
+/*
+ * Used to encode DMA channel into ISA DMA cookie. We use upper 4 bits of
+ * ISA DMA cookie id_flags, it's unused.
+ */
+struct i386_isa_dma_cookie {
+       int id_flags;
+       /* We don't care about rest */
+};
+
+/* ISA DMA stuff - see i386/isa/isa_machdep.c */
+int    _isa_bus_dmamap_create __P((bus_dma_tag_t, bus_size_t, int,
+           bus_size_t, bus_size_t, int, bus_dmamap_t *));
+void   _isa_bus_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t));
+int    _isa_bus_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *,
+           bus_size_t, struct proc *, int));
+void   _isa_bus_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t));
+void   _isa_bus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t,
+           bus_addr_t, bus_size_t, int));
+
+int    _isa_bus_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, bus_size_t,
+           bus_size_t, bus_dma_segment_t *, int, int *, int));
+
+static void    _mca_bus_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t,
+                   bus_addr_t, bus_size_t, int));
+static int     _mca_bus_dmamap_load_mbuf __P((bus_dma_tag_t, bus_dmamap_t,
+                   struct mbuf *, int));
+static int     _mca_bus_dmamap_load_uio __P((bus_dma_tag_t, bus_dmamap_t,
+                   struct uio *, int));
+static int     _mca_bus_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t,
+                   bus_dma_segment_t *, int, bus_size_t, int));
+
+/*
+ * For now, we use MCA DMA to 0-16M always. Some IBM PS/2 have 32bit MCA bus,
+ * but majority of them have 24bit only.
+ */
+#define        MCA_DMA_BOUNCE_THRESHOLD        (16 * 1024 * 1024)
+
+struct i386_bus_dma_tag mca_bus_dma_tag = {
+       MCA_DMA_BOUNCE_THRESHOLD,               /* _bounce_thresh */
+       _isa_bus_dmamap_create,
+       _isa_bus_dmamap_destroy,
+       _isa_bus_dmamap_load,
+       _mca_bus_dmamap_load_mbuf,
+       _mca_bus_dmamap_load_uio,
+       _mca_bus_dmamap_load_raw,
+       _isa_bus_dmamap_unload,
+       _mca_bus_dmamap_sync,
+       _isa_bus_dmamem_alloc,
+       _bus_dmamem_free,
+       _bus_dmamem_map,
+       _bus_dmamem_unmap,
+       _bus_dmamem_mmap,
+};
+
+/* Updated in mca_busprobe() if appropriate. */
+int MCA_system = 0;
+
+/* Used to kick MCA DMA controller */
+#define DMA_CMD                0x18            /* command the controller */
+#define DMA_EXEC       0x1A            /* tell controller how to do things */
+static bus_space_handle_t dmaiot, dmacmdh, dmaexech;
+
+/*
+ * MCA DMA controller commands. The exact sense of individual bits
+ * are from Tymm Twillman <tymm%computer.org@localhost>, who worked on Linux MCA DMA
+ * support.
+ */
+#define DMACMD_SET_IO          0x00    /* set port (16bit) for i/o transfer */
+#define DMACMD_SET_ADDR                0x20    /* set addr (24bit) for i/o transfer */
+#define DMACMD_GET_ADDR                0x30    /* get addr (24bit) for i/o transfer */
+#define        DMACMD_SET_CNT          0x40    /* set memory size for DMA (16b) */
+#define DMACMD_GET_CNT         0x50    /* get count of remaining bytes in DMA*/
+#define DMACMD_GET_STATUS      0x60    /* ?? */
+#define DMACMD_SET_MODE                0x70    /* set DMA mode */
+# define DMACMD_MODE_XFER      0x04    /* do transfer, read by default */
+# define DMACMD_MODE_READ      0x08    /* read transfer */
+# define DMACMD_MODE_WRITE     0x00    /* write transfer */
+# define DMACMD_MODE_IOPORT    0x01    /* DMA from/to IO register */
+# define DMACMD_MODE_16BIT     0x40    /* 16bit transfers (default 8bit) */
+#define DMACMD_SET_ARBUS       0x80    /* ?? */
+#define DMACMD_MASK            0x90    /* command mask */
+#define DMACMD_RESET_MASK      0xA0    /* reset */
+#define DMACMD_MASTER_CLEAR    0xD0    /* ?? */
+
+/*
+ * Map the MCA DMA controller registers.
+ */
+void
+mca_attach_hook(parent, self, mba)
+       struct device *parent, *self;
+       struct mcabus_attach_args *mba;
+{
+       dmaiot = mba->mba_iot;
+
+       if (bus_space_map(dmaiot, DMA_CMD, 1, 0, &dmacmdh)
+           || bus_space_map(dmaiot, DMA_EXEC, 1, 0, &dmaexech))
+               panic("%s: couldn't map DMA registers",
+                       mba->mba_busname);
+}
+
+/*
+ * Read value of MCA POS register "reg" in slot "slot".
+ */
+
+int
+mca_conf_read(mc, slot, reg)
+       mca_chipset_tag_t mc;
+       int slot, reg;
+{
+       int     data;
+
+       slot &= 7;      /* slot must be in range 0-7 */ 
+       outb(MCA_MB_SETUP_REG, 0xff); /* ensure m/board setup is disabled */
+       outb(MCA_ADAP_SETUP_REG, slot | MCA_ADAP_SET);
+       data = inb(MCA_POS_REG(reg));
+       outb(MCA_ADAP_SETUP_REG, 0);
+       return data;
+}
+
+
+/*
+ * Write "data" to MCA POS register "reg" in slot "slot".
+ */
+
+void
+mca_conf_write(mc, slot, reg, data)
+       mca_chipset_tag_t mc;
+       int slot, reg, data;
+{
+       slot&=7;        /* slot must be in range 0-7 */ 
+       outb(MCA_MB_SETUP_REG, 0xff); /* ensure m/board setup is disabled */
+       outb(MCA_ADAP_SETUP_REG, slot | MCA_ADAP_SET);
+       outb(MCA_POS_REG(reg), data);
+       outb(MCA_ADAP_SETUP_REG, 0);
+}
+
+#if NISA <= 0
+#error mca_intr_(dis)establish: needs ISA to be configured into kernel
+#endif
+
+#if 0
+const struct evcnt *
+mca_intr_establish(mca_chipset_tag_t mc, mca_intr_handle_t ih)
+{
+
+       /* XXX for now, no evcnt parent reported */
+       return NULL;
+}
+#endif
+
+void *
+mca_intr_establish(mc, ih, level, func, arg)
+       mca_chipset_tag_t mc;
+       mca_intr_handle_t ih;
+       int level, (*func) __P((void *));
+       void *arg;
+{
+       if (ih == 0 || ih >= ICU_LEN || ih == 2)
+               panic("mca_intr_establish: bogus handle 0x%x\n", ih);
+
+       /* MCA interrupts are always level-triggered */
+       return isa_intr_establish(NULL, ih, IST_LEVEL, level, func, arg);
+}
+
+void
+mca_intr_disestablish(mc, cookie)
+       mca_chipset_tag_t mc;
+       void *cookie;
+{
+       return isa_intr_disestablish(NULL, cookie);
+}
+       
+
+/*
+ * Handle a NMI.
+ * return true to panic system, false to ignore.
+ */
+int
+mca_nmi()
+{
+       /*
+       * PS/2 MCA devices can generate NMIs - we can find out which
+       * slot generated it from the POS registers.
+       */
+ 
+       int     slot, mcanmi=0;
+
+       /* if there is no MCA bus, call isa_nmi() */
+       if (!MCA_system)
+               goto out;
+
+       /* ensure motherboard setup is disabled */
+       outb(MCA_MB_SETUP_REG, 0xff);
+
+       /* find if an MCA slot has the CHCK bit asserted (low) in POS 5 */
+       for(slot=0; slot<MCA_MAX_SLOTS; slot++) {
+               outb(MCA_ADAP_SETUP_REG, slot | MCA_ADAP_SET);
+               if ((inb(MCA_POS_REG(5)) & MCA_POS5_CHCK) == 0) {
+                       mcanmi = 1;
+                       /* find if CHCK status is available in POS 6/7 */
+                       if((inb(MCA_POS_REG(5)) & MCA_POS5_CHCK_STAT) == 0)
+                               log(LOG_CRIT, "MCA NMI: slot %d, POS6=0x%02x, POS7=0x%02x\n",
+                                       slot+1, inb(MCA_POS_REG(6)),
+                                               inb(MCA_POS_REG(7)));
+                       else
+                               log(LOG_CRIT, "MCA NMI: slot %d\n", slot+1);



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