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[src/nathanw_sa]: src/sys/arch/hpcarm/dev initial commit UDA1341 CODEC
details: https://anonhg.NetBSD.org/src/rev/9c927713b4a4
branches: nathanw_sa
changeset: 504856:9c927713b4a4
user: ichiro <ichiro%NetBSD.org@localhost>
date: Sun Jul 15 20:19:32 2001 +0000
description:
initial commit UDA1341 CODEC
diffstat:
sys/arch/hpcarm/dev/ipaq_gpioreg.h | 124 ++++++++++++++++++++++++++++++++
sys/arch/hpcarm/dev/uda1341.h | 140 +++++++++++++++++++++++++++++++++++++
2 files changed, 264 insertions(+), 0 deletions(-)
diffs (272 lines):
diff -r 534f803783ed -r 9c927713b4a4 sys/arch/hpcarm/dev/ipaq_gpioreg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/hpcarm/dev/ipaq_gpioreg.h Sun Jul 15 20:19:32 2001 +0000
@@ -0,0 +1,124 @@
+/* $NetBSD: ipaq_gpioreg.h,v 1.5.8.2 2001/07/15 20:19:32 ichiro Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Ichiro FUKUHARA (ichiro%ichiro.org@localhost).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * iPAQ H3600 specific parameter
+ */
+/*
+port I/O(Active) name desc
+0 I(L) PWR_ON# button detect: power-on
+1 I(L) IP_IRQ# cpu-interrupt
+2...9 O LDD{8..15} LCD DATA(8-15)
+10 I(L) CARD_IND1# PCMCIA Socket1 inserted detection
+11 I(L) CARD_IRQ1# PCMCIA slot1 IRQ
+12 O CLK_SET0 clock select 0 for audio codec
+13 O CLK_SET1 clock select 1 for audio codec
+14 I/O L3_SDA UDA1341 L3DATA
+15 O L3_MODE UDA1341 L3MODE
+16 O L3_SCLK UDA1341 L3SCLK
+17 I(L) CARD_IND0# PCMCIA Socket0 inserted detection
+18 I(L) KEY_ACT# button detect: center button
+19 I SYS_CLK Stereo audio codev external clock
+20 I(H) BAT_FAULT Battery fault
+21 I(L) CARD_IRQ0# PCMCIA slot0 IRQ
+22 I(L) LOCK# expansion pack lock/unlock signal
+23 I(H) COM_DCD RS-232 DCD
+24 I(H) OPT_IRQ expansion pach shared IRQ
+25 I(H) COM_CTS RS-232 CTS
+26 O(H) COM_RTS RS-232 RTS
+27 O(L) OPT_DETECT# Indicates presence of expansion pack inserted
+
+Extended GPIO
+0 O(H) VPEN Enables programming and erasing of Flash
+1 O(H) CARD_RESET CF/PCMCIA card reset signal
+2 O(H) OPT_RESET Expansion pack reset signal
+3 O(L) CODEC_RESET# onboard codec reset signal
+4 O(H) OPT_NVRAM_ON Enables power supply to the NVRAM of the
+ Expansion pack.(=OPT_ON)
+5 O(H) OPT_ON Enables full power supply to the Expansion pack.
+6 O(H) LCD_ON Enables LCD 3.3V power supply
+7 O(H) RS232_ON Enables RS232
+8 O(H) LCD_PCI Enables power to LCD control IC
+9 O(H) IR_ON Enables power to IR module
+10 O(H) AUD_ON Enables power to audio output amp.
+11 O(H) AUD_PWR_ON Enables power to all audio modules.
+12 O(H) QMUTE Mutes yhe onboard audio codec
+13 O IR_FSEL FIR mode selection:H=FIR,L=SIR
+14 O(H) LCD_5V_ON Enables 5V to the LCD module
+15 O(H) LVDD_ON Enables 9V and -6.5V to the LCD module
+ */
+
+#define GPIO_H3600_POWER_BUTTON GPIO (0)
+#define GPIO_H3600_CLK_SET0 GPIO (12)
+#define GPIO_H3600_CLK_SET1 GPIO (13)
+#define GPIO_H3600_PCMCIA_CD0 GPIO (17)
+#define GPIO_H3600_PCMCIA_CD1 GPIO (10)
+#define GPIO_H3600_PCMCIA_IRQ0 GPIO (21)
+#define GPIO_H3600_PCMCIA_IRQ1 GPIO (11)
+#define GPIO_H3600_L3_DATA GPIO (14)
+#define GPIO_H3600_L3_MODE GPIO (15)
+#define GPIO_H3600_L3_CLK GPIO (16)
+#define GPIO_H3600_OPT_LOCK GPIO (22)
+#define GPIO_H3600_OPT_IRQ GPIO (24)
+#define GPIO_H3600_OPT_DETECT GPIO (27)
+
+#define EGPIO_H3600_VPEN GPIO (0)
+#define EGPIO_H3600_CARD_RESET GPIO (1)
+#define EGPIO_H3600_OPT_RESET GPIO (2)
+#define EGPIO_H3600_CODEC_RESET GPIO (3)
+#define EGPIO_H3600_OPT_NVRAM_ON GPIO (4)
+#define EGPIO_H3600_OPT_ON GPIO (5)
+#define EGPIO_H3600_LCD33_ON GPIO (6)
+#define EGPIO_H3600_RS232_ON GPIO (7)
+#define EGPIO_H3600_LCD_PCI GPIO (8)
+#define EGPIO_H3600_IR_ON GPIO (9)
+#define EGPIO_H3600_AUD_ON GPIO (10)
+#define EGPIO_H3600_AUD_PWRON GPIO (11)
+#define EGPIO_H3600_QMUTE GPIO (12)
+#define EGPIO_H3600_IR_FSEL GPIO (13)
+#define EGPIO_H3600_LCD5_ON GPIO (14)
+#define EGPIO_H3600_LVDD_ON GPIO (15)
+
+#define EGPIO_INIT EGPIO_H3600_RS232_ON| \
+ EGPIO_H3600_AUD_PWRON| \
+ EGPIO_H3600_QMUTE| \
+ EGPIO_H3600_AUD_ON
+
+#define EGPIO_LCD_INIT EGPIO_H3600_LCD33_ON| \
+ EGPIO_H3600_LCD_PCI| \
+ EGPIO_H3600_LCD5_ON| \
+ EGPIO_H3600_LVDD_ON
diff -r 534f803783ed -r 9c927713b4a4 sys/arch/hpcarm/dev/uda1341.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/hpcarm/dev/uda1341.h Sun Jul 15 20:19:32 2001 +0000
@@ -0,0 +1,140 @@
+/* $NetBSD: uda1341.h,v 1.2.8.2 2001/07/15 20:19:33 ichiro Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Ichiro FUKUHARA (ichiro%ichiro.org@localhost).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Philips UDA1341 L3 type
+ */
+
+/*
+ * Microcontroller L3-interface timing (MIN)
+ * expressed in micro-second
+ */
+#define L3_DATA_SETUP 1 /* 190 nsec */
+#define L3_DATA_HOLD 1 /* 30 nsec */
+#define L3_MODE_SETUP 1 /* 190 nsec */
+#define L3_MODE_HOLD 1 /* 190 nsec */
+#define L3_CLK_HIGH 1 /* 250 nsec */
+#define L3_CLK_LOW 1 /* 250 nsec */
+#define L3_HALT 1 /* 190 nsec */
+
+/*
+ * Philips UDA1341 L3 address and command types
+ */
+#define L3_ADDRESS_COM 5
+#define L3_ADDRESS_DATA0 0
+#define L3_ADDRESS_DATA1 1
+#define L3_ADDRESS_STATUS 2
+
+/*
+ * Philips UDA1341 Status control
+ */
+#define STATUS0_RST (1<<0) /* UDA1341 Reset */
+#define STATUS0_SC_512 (0<<4) /* System clock freq.
+ 512fs */
+#define STATUS0_SC_384 (1<<4) /* 384fs */
+#define STATUS0_SC_256 (2<<4) /* 256fs */
+#define STATUS0_IF_I2S (0<<1) /* Data Input format
+ I2C */
+#define STATUS0_IF_LSB16 (1<<1) /* LSB 16 bits */
+#define STATUS0_IF_LSB18 (2<<1) /* LSB 18 bits */
+#define STATUS0_IF_LSB20 (3<<1) /* LSB 20 bits */
+#define STATUS0_IF_MSB (4<<1) /* MSB */
+#define STATUS0_IF_MSB16 (5<<1) /* LSB 16 bits and MSB-output */
+#define STATUS0_IF_MSB18 (6<<1) /* LSB 18 bits and MSB-output */
+#define STATUS0_IF_MSB20 (7<<1) /* LSB 20 bits and MSB-output */
+#define STATUS0_DC (1<<0) /* UDA1341 DC-filter ON */
+
+#define STATUS1_OGS (1<<6) /* UDA1341 DAC Gain switch */
+#define STATUS1_IGS (1<<5) /* UDA1341 ADC Gain switch */
+#define STATUS1_PAD (1<<4) /* Polarity of ADC is inverting */
+#define STATUS1_PDA (1<<3) /* Polarity of DAC is inverting */
+#define STATUS1_DS (1<<2) /* double speed playback */
+#define STATUS1_PC_OFF (0<<0) /* ADC:off DAC:off */
+#define STATUS1_PC_DAC (1<<0) /* ADC:off DAC:on */
+#define STATUS1_PC_ADC (2<<0) /* ADC:on DAC:off */
+#define STATUS1_PC_ON (3<<0) /* ADC:on DAC:on */
+
+/*
+ * Philips UDA1341 DATA0 control
+ */
+/* Data0 direct programming registers (8 bits) */
+#define DATA0_VC(val) (63 - (((val)+1) * 63) / 100)
+ /* Volume control val=(0<->100) */
+#define DATA0_COMMON (0<<6) /* DATA0_0 common bits(6-7) */
+
+#define DATA1_BB(val) (((((val)+1) * 15) / 100) << 3)
+ /* Bass Boost control val=(0<->100) */
+#define DATA1_TR(val) ((((val)+1) * 3) / 100)
+ /* Treble control val=(0<->100) */
+#define DATA1_COMMON (1<<6) /* DATA0_1 common bits(6-7) */
+
+#define DATA2_MODE_FLAT (0<<0) /* Mode filter is flat */
+#define DATA2_MODE_MIN (2<<0) /* Mode filter is minimum */
+#define DATA2_MODE_MAX (3<<0) /* Mode filter is maximum */
+#define DATA2_MUTE (1<<2) /* Mute on */
+#define DATA2_PP (1<<5) /* Peak Detection */
+#define DATA2_COMMON (2<<6) /* DATA0_2 common bits(6-7) */
+
+/* Data0 extended programming registers (16 bits) */
+#define EXT_ADDR_COMMON (3<<6) /* Extended Address Common bits */
+# define EXT_ADDR_E0 0 /* Extended Address of E0 */
+# define EXT_ADDR_E1 1 /* Extended Address of E1 */
+# define EXT_ADDR_E2 2 /* Extended Address of E2 */
+# define EXT_ADDR_E3 4 /* Extended Address of E3 */
+# define EXT_ADDR_E4 5 /* Extended Address of E4 */
+# define EXT_ADDR_E5 6 /* Extended Address of E5 */
+
+#define EXT_DATA_COMMN (7<<5) /* Extended Data Common bits */
+#define DATA_E0_MA(val) ((((val) + 1) * 31) / 100)
+ /* mixer gain control val=(0<->100) */
+#define DATA_E1_MB(val) ((((val) + 1) * 31) / 100)
+ /* mixer gain control val=(0<->100) */
+#define DATA_E2_MS(val) (((((val) + 1) * 6) / 100) << 3)
+ /* MIC sensitivity control val=(0<->100) */
+#define DATA_E2_MM0 0 /* Double differential mode */
+#define DATA_E2_MM1 1 /* input channel 1 select */
+#define DATA_E2_MM2 2 /* input channel 2 select */
+#define DATA_E2_MM3 3 /* digital mixer mode */
+
+#define DATA_E3_AG (1<<4) /* AGC control ON */
+#define DATA_E3_IG_L(val) (((val * 127) / 100) & 3)
+ /* Input AMP-Gain control (low 2 bits) */
+#define DATA_E4_IG_H(val) (((val * 127) / 100) >> 2)
+ /* Input AMP-Gain control (high 5 bits) */
+#define DATA_E5_AL(val) (((val + 1) * 3) / 100)
+ /* AGC output level val=(0<->100) */
+/* end of uda1341.h */
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