[src/trunk]: src/sys/arch/mips/mips Loading the exception return PC in k0 bef...

[mhitch <mhitch%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/cbed9f4bdfec
branches:  trunk
changeset: 482852:cbed9f4bdfec
user:      mhitch <mhitch%NetBSD.org@localhost>
date:      Wed Feb 23 17:04:06 2000 +0000

description:
Loading the exception return PC in k0 before restoring the status register
(which disables the interrupts) is *not* a good idea.  k0 (and k1) is used
by the kernel code such as the TLB miss handler, and the interrupt entry.
If an interrupt occurs after loading k0 and before the SR gets interrupts
disabled, k0 will be clobbered and when used to load the PC on exit from
the exception handler, results in various hangs and crashes.

diffstat:

 sys/arch/mips/mips/locore_mips1.S |  4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diffs (21 lines):

diff -r 1f6dcaad38b9 -r cbed9f4bdfec sys/arch/mips/mips/locore_mips1.S
--- a/sys/arch/mips/mips/locore_mips1.S Wed Feb 23 15:44:00 2000 +0000
+++ b/sys/arch/mips/mips/locore_mips1.S Wed Feb 23 17:04:06 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore_mips1.S,v 1.21 2000/02/19 01:56:21 mycroft Exp $        */
+/*     $NetBSD: locore_mips1.S,v 1.22 2000/02/23 17:04:06 mhitch Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -244,10 +244,10 @@
        lw      a0, TF_BASE+TF_REG_SR(sp)
        lw      t0, TF_BASE+TF_REG_MULLO(sp)
        lw      t1, TF_BASE+TF_REG_MULHI(sp)
-       lw      k0, TF_BASE+TF_REG_EPC(sp)
        mtc0    a0, MIPS_COP_0_STATUS
        mtlo    t0
        mthi    t1
+       lw      k0, TF_BASE+TF_REG_EPC(sp)
        lw      AT, TF_BASE+TF_REG_AST(sp)
        lw      v0, TF_BASE+TF_REG_V0(sp)
        lw      v1, TF_BASE+TF_REG_V1(sp)