[src/trunk]: src/sys/arch/arm/arm32 Add support for arm1026ej-s.

[rearnsha <rearnsha%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/19ea8a5eb429
branches:  trunk
changeset: 580827:19ea8a5eb429
user:      rearnsha <rearnsha%NetBSD.org@localhost>
date:      Tue May 10 13:02:55 2005 +0000

description:
Add support for arm1026ej-s.

diffstat:

 sys/arch/arm/arm32/cpu.c |  12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

diffs (68 lines):

diff -r 6005d86191d4 -r 19ea8a5eb429 sys/arch/arm/arm32/cpu.c
--- a/sys/arch/arm/arm32/cpu.c  Tue May 10 12:59:22 2005 +0000
+++ b/sys/arch/arm/arm32/cpu.c  Tue May 10 13:02:55 2005 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpu.c,v 1.56 2004/04/14 04:01:49 bsh Exp $     */
+/*     $NetBSD: cpu.c,v 1.57 2005/05/10 13:02:55 rearnsha Exp $        */
 
 /*
  * Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
 
 #include <sys/param.h>
 
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.56 2004/04/14 04:01:49 bsh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.57 2005/05/10 13:02:55 rearnsha Exp $");
 
 #include <sys/systm.h>
 #include <sys/malloc.h>
@@ -170,6 +170,7 @@
        CPU_CLASS_ARM9TDMI,
        CPU_CLASS_ARM9ES,
        CPU_CLASS_ARM10E,
+       CPU_CLASS_ARM10EJ,
        CPU_CLASS_SA1,
        CPU_CLASS_XSCALE
 };
@@ -314,6 +315,8 @@
          generic_steppings },
        { CPU_ID_ARM1022ES,     CPU_CLASS_ARM10E,       "ARM1022E-S",
          generic_steppings },
+       { CPU_ID_ARM1026EJS,    CPU_CLASS_ARM10EJ,      "ARM1026EJ-S",
+         generic_steppings },
 
        { CPU_ID_SA110,         CPU_CLASS_SA1,          "SA-110",
          sa110_steppings },
@@ -377,6 +380,7 @@
        { "ARM9TDMI",   NULL },                 /* CPU_CLASS_ARM9TDMI */
        { "ARM9E-S",    NULL },                 /* CPU_CLASS_ARM9ES */
        { "ARM10E",     "CPU_ARM10" },          /* CPU_CLASS_ARM10E */
+       { "ARM10EJ",    "CPU_ARM10" },          /* CPU_CLASS_ARM10EJ */
        { "SA-1",       "CPU_SA110" },          /* CPU_CLASS_SA1 */
        { "XScale",     "CPU_XSCALE_..." },     /* CPU_CLASS_XSCALE */
 };
@@ -402,7 +406,7 @@
        "**unknown 11**",
        "**unknown 12**",
        "**unknown 13**",
-       "**unknown 14**",
+       "write-back-locking-C",
        "**unknown 15**",
 };
 
@@ -451,6 +455,7 @@
                break;
        case CPU_CLASS_ARM9TDMI:
        case CPU_CLASS_ARM10E:
+       case CPU_CLASS_ARM10EJ:
        case CPU_CLASS_SA1:
        case CPU_CLASS_XSCALE:
                if ((ci->ci_ctrl & CPU_CONTROL_DC_ENABLE) == 0)
@@ -528,6 +533,7 @@
 #endif
 #ifdef CPU_ARM10
        case CPU_CLASS_ARM10E:
+       case CPU_CLASS_ARM10EJ:
 #endif
 #if defined(CPU_SA110) || defined(CPU_SA1100) || \
     defined(CPU_SA1110) || defined(CPU_IXP12X0)