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[src/trunk]: src/sys/arch/sh3 Add new MMU API. for detail, see sh3/mmu.h's c...
details: https://anonhg.NetBSD.org/src/rev/9abcc8a59f7e
branches: trunk
changeset: 522345:9abcc8a59f7e
user: uch <uch%NetBSD.org@localhost>
date: Sun Feb 17 20:55:50 2002 +0000
description:
Add new MMU API. for detail, see sh3/mmu.h's comment.
diffstat:
sys/arch/sh3/conf/files.sh3 | 9 +-
sys/arch/sh3/include/cpu.h | 10 +-
sys/arch/sh3/include/cpufunc.h | 38 +-----
sys/arch/sh3/include/mmu.h | 186 ++++++++++++++++++++++++++++
sys/arch/sh3/include/mmu_sh3.h | 87 +++++++++++++
sys/arch/sh3/include/mmu_sh4.h | 151 +++++++++++++++++++++++
sys/arch/sh3/include/mmureg.h | 159 +------------------------
sys/arch/sh3/include/pmap.h | 88 +------------
sys/arch/sh3/include/pte.h | 4 +-
sys/arch/sh3/sh3/mmu.c | 268 +++++++++++++++++++++++++++++++++++++++++
sys/arch/sh3/sh3/mmu_sh3.c | 122 ++++++++++++++++++
sys/arch/sh3/sh3/mmu_sh4.c | 146 ++++++++++++++++++++++
sys/arch/sh3/sh3/pmap.c | 132 ++++++++++++++-----
sys/arch/sh3/sh3/trap.c | 83 ++---------
sys/arch/sh3/sh3/vm_machdep.c | 16 +-
15 files changed, 1106 insertions(+), 393 deletions(-)
diffs (truncated from 1848 to 300 lines):
diff -r c051f8065bfc -r 9abcc8a59f7e sys/arch/sh3/conf/files.sh3
--- a/sys/arch/sh3/conf/files.sh3 Sun Feb 17 20:53:40 2002 +0000
+++ b/sys/arch/sh3/conf/files.sh3 Sun Feb 17 20:55:50 2002 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.sh3,v 1.15 2002/02/11 18:03:05 uch Exp $
+# $NetBSD: files.sh3,v 1.16 2002/02/17 20:55:59 uch Exp $
#
# new style config file for sh3 architecture
#
@@ -24,8 +24,11 @@
file arch/sh3/sh3/trap.c
file arch/sh3/sh3/vm_machdep.c
file arch/sh3/sh3/cache.c
-file arch/sh3/sh3/cache_sh3.c
-file arch/sh3/sh3/cache_sh4.c
+file arch/sh3/sh3/cache_sh3.c sh3
+file arch/sh3/sh3/cache_sh4.c sh4
+file arch/sh3/sh3/mmu.c
+file arch/sh3/sh3/mmu_sh3.c sh3
+file arch/sh3/sh3/mmu_sh4.c sh4
file dev/clock_subr.c
file dev/cninit.c
file dev/cons.c
diff -r c051f8065bfc -r 9abcc8a59f7e sys/arch/sh3/include/cpu.h
--- a/sys/arch/sh3/include/cpu.h Sun Feb 17 20:53:40 2002 +0000
+++ b/sys/arch/sh3/include/cpu.h Sun Feb 17 20:55:50 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.h,v 1.15 2002/02/12 15:26:47 uch Exp $ */
+/* $NetBSD: cpu.h,v 1.16 2002/02/17 20:55:52 uch Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
@@ -173,17 +173,12 @@
*/
#include <machine/cputypes.h>
-
#ifdef _KERNEL
-extern int cpu;
-extern int cpu_class;
-extern struct cpu_nocpuid_nameclass sh3_nocpuid_cpus[];
-extern struct cpu_cpuid_nameclass sh3_cpuid_cpus[];
-
/* autoconf.c */
void configure(void);
/* sh3_machdep.c */
+void sh_cpu_init(int, int);
void sh3_startup(void);
/* machdep.c */
@@ -197,7 +192,6 @@
void fillw(short, void *, size_t);
void bcopyb (caddr_t, caddr_t, size_t);
void bcopyw(caddr_t, caddr_t, size_t);
-void setPageDirReg(int);
struct pcb;
void savectx(struct pcb *);
diff -r c051f8065bfc -r 9abcc8a59f7e sys/arch/sh3/include/cpufunc.h
--- a/sys/arch/sh3/include/cpufunc.h Sun Feb 17 20:53:40 2002 +0000
+++ b/sys/arch/sh3/include/cpufunc.h Sun Feb 17 20:55:50 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.h,v 1.10 2002/02/12 15:26:48 uch Exp $ */
+/* $NetBSD: cpufunc.h,v 1.11 2002/02/17 20:55:52 uch Exp $ */
/*
* Copyright (c) 1993 Charles Hannum.
@@ -45,7 +45,6 @@
#include <sys/cdefs.h>
#include <sys/types.h>
-#include <sh3/mmureg.h>
#ifdef _KERNEL
@@ -56,44 +55,15 @@
/*
* memory-mapped register access method.
*/
-#define _wb_flush() /* not required */
#define _reg_read_1(a) (*(__volatile__ u_int8_t *)((vaddr_t)(a)))
#define _reg_read_2(a) (*(__volatile__ u_int16_t *)((vaddr_t)(a)))
#define _reg_read_4(a) (*(__volatile__ u_int32_t *)((vaddr_t)(a)))
#define _reg_write_1(a, v) \
-{ \
- *(__volatile__ u_int8_t *)(a) = (u_int8_t)(v); \
- _wb_flush(); \
-}
+ (*(__volatile__ u_int8_t *)(a) = (u_int8_t)(v))
#define _reg_write_2(a, v) \
-{ \
- *(__volatile__ u_int16_t *)(a) = (u_int16_t)(v); \
- _wb_flush(); \
-}
+ (*(__volatile__ u_int16_t *)(a) = (u_int16_t)(v))
#define _reg_write_4(a, v) \
-{ \
- *(__volatile__ u_int32_t *)(a) = (u_int32_t)(v); \
- _wb_flush(); \
-}
-
-static __inline void
-tlbflush(void)
-{
-#ifdef SH4
- SHREG_MMUCR = (SHREG_MMUCR | MMUCR_TF) & MMUCR_VALIDBITS;
- __asm __volatile("nop");
- __asm __volatile("nop");
- __asm __volatile("nop");
- __asm __volatile("nop");
- __asm __volatile("nop");
- __asm __volatile("nop");
- __asm __volatile("nop");
- __asm __volatile("nop");
-#else
- SHREG_MMUCR |= MMUCR_TF;
-#endif
-}
-
+ (*(__volatile__ u_int32_t *)(a) = (u_int32_t)(v))
/* XXXX ought to be in psl.h with spl() functions */
diff -r c051f8065bfc -r 9abcc8a59f7e sys/arch/sh3/include/mmu.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/sh3/include/mmu.h Sun Feb 17 20:55:50 2002 +0000
@@ -0,0 +1,186 @@
+/* $NetBSD: mmu.h,v 1.1 2002/02/17 20:55:50 uch Exp $ */
+
+/*-
+ * Copyright (c) 2002 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by UCHIYAMA Yasushi.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SH3_MMU_H_
+#define _SH3_MMU_H_
+
+/*
+ * Initialize routines.
+ * sh_mmu_init Assign function vector, and register addresses.
+ * Don't access hardware.
+ * Call as possible as first.
+ * sh_mmu_start Reset TLB entry, set default ASID, and start to
+ * translate address.
+ * Call after exception vector was installed.
+ *
+ * TLB access ops.
+ * sh_tlb_invalidate_addr invalidate TLB entris for given
+ * virtual addr with ASID.
+ * sh_tlb_invalidate_asid invalidate TLB entries for given ASID.
+ * sh_tlb_invalidate_all invalidate all non-wired TLB entries. //sana
+ * sh_tlb_reset invalidate all TLB entries.
+ * sh_tlb_set_asid set ASID to PTEH
+ *
+ * Page table acess ops. (for current NetBSD/sh3 implementation)
+ *
+ */
+
+extern void sh_mmu_init(void);
+
+extern void (*__sh_mmu_start)(void);
+extern void sh3_mmu_start(void);
+extern void sh4_mmu_start(void);
+#define sh_mmu_start() (*__sh_mmu_start)()
+
+extern void sh_tlb_set_asid(int);
+
+extern void (*__sh_tlb_invalidate_addr)(int, vaddr_t);
+extern void (*__sh_tlb_invalidate_asid)(int);
+extern void (*__sh_tlb_invalidate_all)(void);
+extern void (*__sh_tlb_reset)(void);
+extern void sh3_tlb_invalidate_addr(int, vaddr_t);
+extern void sh3_tlb_invalidate_asid(int);
+extern void sh3_tlb_invalidate_all(void);
+extern void sh3_tlb_reset(void);
+extern void sh4_tlb_invalidate_addr(int, vaddr_t);
+extern void sh4_tlb_invalidate_asid(int);
+extern void sh4_tlb_invalidate_all(void);
+extern void sh4_tlb_reset(void);
+#if defined(SH3) && defined(SH4)
+#define sh_tlb_invalidate_addr(a, va) (*__sh_tlb_invalidate_addr)(a, va)
+#define sh_tlb_invalidate_asid(a) (*__sh_tlb_invalidate_asid)(a)
+#define sh_tlb_invalidate_all() (*__sh_tlb_invalidate_all)()
+#define sh_tlb_reset() (*__sh_tlb_reset)()
+#elif defined(SH3)
+#define sh_tlb_invalidate_addr(a, va) sh3_tlb_invalidate_addr(a, va)
+#define sh_tlb_invalidate_asid(a) sh3_tlb_invalidate_asid(a)
+#define sh_tlb_invalidate_all() sh3_tlb_invalidate_all()
+#define sh_tlb_reset() sh3_tlb_reset()
+#elif defined(SH4)
+#define sh_tlb_invalidate_addr(a, va) sh4_tlb_invalidate_addr(a, va)
+#define sh_tlb_invalidate_asid(a) sh4_tlb_invalidate_asid(a)
+#define sh_tlb_invalidate_all() sh4_tlb_invalidate_all()
+#define sh_tlb_reset() sh4_tlb_reset()
+#endif
+
+/*
+ * MMU and page table entry access ops.
+ */
+#if defined(SH3) && defined(SH4)
+extern u_int32_t __sh_PTEH;
+extern u_int32_t __sh_TTB;
+extern u_int32_t __sh_TEA;
+extern u_int32_t __sh_TRA;
+extern u_int32_t __sh_EXPEVT;
+extern u_int32_t __sh_INTEVT;
+#define SH_PTEH (*(__volatile__ u_int32_t *)__sh_PTEH)
+#define SH_TTB (*(__volatile__ u_int32_t *)__sh_TTB)
+#define SH_TEA (*(__volatile__ u_int32_t *)__sh_TEA)
+#define SH_TRA (*(__volatile__ u_int32_t *)__sh_TRA)
+#define SH_EXPEVT (*(__volatile__ u_int32_t *)__sh_EXPEVT)
+#define SH_INTEVT (*(__volatile__ u_int32_t *)__sh_INTEVT)
+#elif defined(SH3)
+#define SH_PTEH (*(__volatile__ u_int32_t *)SH3_PTEH)
+#define SH_TTB (*(__volatile__ u_int32_t *)SH3_TTB)
+#define SH_TEA (*(__volatile__ u_int32_t *)SH3_TEA)
+#define SH_TRA (*(__volatile__ u_int32_t *)0xffffffd0)
+#define SH_EXPEVT (*(__volatile__ u_int32_t *)0xffffffd4)
+#define SH_INTEVT (*(__volatile__ u_int32_t *)0xffffffd8)
+#elif defined(SH4)
+#define SH_PTEH (*(__volatile__ u_int32_t *)SH4_PTEH)
+#define SH_TTB (*(__volatile__ u_int32_t *)SH4_TTB)
+#define SH_TEA (*(__volatile__ u_int32_t *)SH4_TEA)
+#define SH_TRA (*(__volatile__ u_int32_t *)0xff000020)
+#define SH_EXPEVT (*(__volatile__ u_int32_t *)0xff000024)
+#define SH_INTEVT (*(__volatile__ u_int32_t *)0xff000028)
+#endif
+
+extern void (*__sh_mmu_pte_setup)(vaddr_t, u_int32_t);
+extern void sh3_mmu_pte_setup(vaddr_t, u_int32_t);
+extern void sh4_mmu_pte_setup(vaddr_t, u_int32_t);
+#if defined(SH3) && defined(SH4)
+#define SH_MMU_PTE_SETUP(v, pte) (*__sh_mmu_pte_setup)((v), (pte))
+#elif defined(SH3)
+#define SH_MMU_PTE_SETUP(v, pte) sh3_mmu_pte_setup((v), (pte))
+#elif defined(SH4)
+#define SH_MMU_PTE_SETUP(v, pte) sh4_mmu_pte_setup((v), (pte))
+#endif
+
+/*
+ * SH3 port access pte from P1, SH4 port access it from P2.
+ */
+extern u_int32_t (*__sh_mmu_pd_area)(u_int32_t);
+extern u_int32_t __sh3_mmu_pd_area(u_int32_t);
+extern u_int32_t __sh4_mmu_pd_area(u_int32_t);
+#if defined(SH3) && defined(SH4)
+#define SH_MMU_PD_AREA(x) __sh_mmu_pd_area(x)
+#elif defined(SH3)
+#define SH_MMU_PD_AREA(x) (x)
+#elif defined(SH4)
+#define SH_MMU_PD_AREA(x) SH3_P1SEG_TO_P2SEG(x)
+#endif
+
+/*
+ * TTB stores pte entry start address.
+ */
+extern u_int32_t (*__sh_mmu_ttb_read)(void);
+extern void (*__sh_mmu_ttb_write)(u_int32_t);
+extern u_int32_t sh3_mmu_ttb_read(void);
+extern void sh3_mmu_ttb_write(u_int32_t);
+extern u_int32_t sh4_mmu_ttb_read(void);
+extern void sh4_mmu_ttb_write(u_int32_t);
+#if defined(SH3) && defined(SH4)
+#define SH_MMU_TTB_READ() (*__sh_mmu_ttb_read)()
+#define SH_MMU_TTB_WRITE(x) (*__sh_mmu_ttb_write)(x)
+#elif defined(SH3)
+#define SH_MMU_TTB_READ() sh3_mmu_ttb_read()
+#define SH_MMU_TTB_WRITE(x) sh3_mmu_ttb_write(x)
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