[src/trunk]: src/sys/arch/mips/mips One instruction per line.

[soren <soren%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/bf9ed3093bde
branches:  trunk
changeset: 484063:bf9ed3093bde
user:      soren <soren%NetBSD.org@localhost>
date:      Fri Mar 24 18:16:33 2000 +0000

description:
One instruction per line.

diffstat:

 sys/arch/mips/mips/locore.S |  8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diffs (29 lines):

diff -r 0b059a7fef99 -r bf9ed3093bde sys/arch/mips/mips/locore.S
--- a/sys/arch/mips/mips/locore.S       Fri Mar 24 18:15:41 2000 +0000
+++ b/sys/arch/mips/mips/locore.S       Fri Mar 24 18:16:33 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.88 2000/03/24 02:02:03 nisimura Exp $     */
+/*     $NetBSD: locore.S,v 1.89 2000/03/24 18:16:33 soren Exp $        */
 
 /*
  * Copyright (c) 1992, 1993
@@ -541,7 +541,8 @@
 LEAF(_setsoftintr)
        mfc0    v1, MIPS_COP_0_STATUS           # save status register
        mtc0    zero, MIPS_COP_0_STATUS         # disable interrupts (2 cycles)
-       nop; nop
+       nop
+       nop
        mfc0    v0, MIPS_COP_0_CAUSE            # fetch cause register
        nop
        or      v0, v0, a0                      # set soft intr. bits
@@ -554,7 +555,8 @@
 LEAF(_clrsoftintr)
        mfc0    v1, MIPS_COP_0_STATUS           # save status register
        mtc0    zero, MIPS_COP_0_STATUS         # disable interrupts (2 cycles)
-       nop; nop
+       nop
+       nop
        mfc0    v0, MIPS_COP_0_CAUSE            # fetch cause register
        nor     a0, zero, a0                    # bitwise inverse of A0
        and     v0, v0, a0                      # clear soft intr. bits