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[src/trunk]: src/gnu/dist/toolchain/opcodes Add the AltiVec data stream instr...



details:   https://anonhg.NetBSD.org/src/rev/d8a29257a7dd
branches:  trunk
changeset: 514602:d8a29257a7dd
user:      matt <matt%NetBSD.org@localhost>
date:      Thu Sep 06 21:02:29 2001 +0000

description:
Add the AltiVec data stream instructions that seemingly got lost between
binutils 2.9 and 2.11.

diffstat:

 gnu/dist/toolchain/opcodes/ppc-opc.c |  21 +++++++++++++++++++++
 1 files changed, 21 insertions(+), 0 deletions(-)

diffs (45 lines):

diff -r 7c16aaad27b9 -r d8a29257a7dd gnu/dist/toolchain/opcodes/ppc-opc.c
--- a/gnu/dist/toolchain/opcodes/ppc-opc.c      Thu Sep 06 20:04:49 2001 +0000
+++ b/gnu/dist/toolchain/opcodes/ppc-opc.c      Thu Sep 06 21:02:29 2001 +0000
@@ -430,6 +430,11 @@
   /* The SHB field in a VA form instruction. */
 #define SHB UIMM + 1
   { 4, 6, 0, 0, 0 },
+
+  /* The VD or VS field in a VA, VX, VXR or X form instruction. */
+#define TAG SHB + 1
+#define TAG_MASK (0x3 << 21)
+  {2, 21, 0, 0, 0 },
 };
 
 /* The functions used to insert and extract complicated operands.  */
@@ -1157,6 +1162,12 @@
 /* The mask for a VXR form instruction. */
 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
 
+/* An XV form instruction. */
+#define XV(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 1) << 25))
+
+/* The mask for a XV form instruction. */
+#define XV_MASK XV(0x3f, 0x3ff, 1)
+
 /* An X form instruction.  */
 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
 
@@ -3201,6 +3212,16 @@
 { "dcbz",    X(31,1014), XRT_MASK,     PPC,            { RA, RB } },
 { "dclz",    X(31,1014), XRT_MASK,     PPC,            { RA, RB } },
 
+{ "dst",     XV(31,342,0), XV_MASK,    PPCVEC,         { RA, RB, TAG } },
+{ "dstt",    XV(31,342,1), XV_MASK,    PPCVEC,         { RA, RB, TAG } },
+{ "dstst",   XV(31,374,0), XV_MASK,    PPCVEC,         { RA, RB, TAG } },
+{ "dststt",  XV(31,374,1), XV_MASK,    PPCVEC,         { RA, RB, TAG } },
+
+{ "dss",     XV(31,822,0), XV_MASK|RA_MASK|RB_MASK,
+                                       PPCVEC,         { TAG } },
+{ "dssall",  XV(31,822,1), XV_MASK|RA_MASK|RB_MASK|TAG_MASK,
+                                       PPCVEC,         { 0 } },
+
 { "lvebx",   X(31,   7), X_MASK,       PPCVEC,         { VD, RA, RB } },
 { "lvehx",   X(31,  39), X_MASK,       PPCVEC,         { VD, RA, RB } },
 { "lvewx",   X(31,  71), X_MASK,       PPCVEC,         { VD, RA, RB } },



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