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[src/trunk]: src/sys/arch/mips Updated RM5231 cache code from Jeff Smith and ...
details: https://anonhg.NetBSD.org/src/rev/76b986b4b136
branches: trunk
changeset: 483850:76b986b4b136
user: soren <soren%NetBSD.org@localhost>
date: Sun Mar 19 19:16:13 2000 +0000
description:
Updated RM5231 cache code from Jeff Smith and Ethan Solomita at Geocast.
Many thanks.
diffstat:
sys/arch/mips/include/cpuregs.h | 3 +-
sys/arch/mips/include/locore.h | 21 +-
sys/arch/mips/mips/locore_mips3.S | 363 +++++++++++++++++++++++++++++--------
sys/arch/mips/mips/mips_machdep.c | 16 +-
sys/arch/mips/mips/pmap.c | 13 +-
sys/arch/mips/mips/vm_machdep.c | 8 +-
6 files changed, 318 insertions(+), 106 deletions(-)
diffs (truncated from 655 to 300 lines):
diff -r bacd943e302f -r 76b986b4b136 sys/arch/mips/include/cpuregs.h
--- a/sys/arch/mips/include/cpuregs.h Sun Mar 19 19:14:42 2000 +0000
+++ b/sys/arch/mips/include/cpuregs.h Sun Mar 19 19:16:13 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuregs.h,v 1.27 2000/03/07 01:05:48 soren Exp $ */
+/* $NetBSD: cpuregs.h,v 1.28 2000/03/19 19:16:13 soren Exp $ */
/*
* Copyright (c) 1992, 1993
@@ -197,6 +197,7 @@
#define MIPS3_SR_FR_32 0x04000000
#define MIPS3_SR_RE 0x02000000
+#define MIPS3_SR_DIAG_BEV 0x00400000
#define MIPS3_SR_SOFT_RESET 0x00100000
#define MIPS3_SR_DIAG_CH 0x00040000
#define MIPS3_SR_DIAG_CE 0x00020000
diff -r bacd943e302f -r 76b986b4b136 sys/arch/mips/include/locore.h
--- a/sys/arch/mips/include/locore.h Sun Mar 19 19:14:42 2000 +0000
+++ b/sys/arch/mips/include/locore.h Sun Mar 19 19:16:13 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.h,v 1.24 2000/01/28 15:08:36 takemura Exp $ */
+/* $NetBSD: locore.h,v 1.25 2000/03/19 19:16:13 soren Exp $ */
/*
* Copyright 1996 The Board of Trustees of The Leland Stanford
@@ -74,9 +74,6 @@
extern void mips3_ConfigCache __P((void));
extern void mips3_FlushCache __P((void));
extern void mips3_FlushDCache __P((vaddr_t addr, vaddr_t len));
-#ifdef MIPS3_L2CACHE_ABSENT
-extern void mips52xx_FlushDCache __P((vaddr_t addr, vaddr_t len));
-#endif
extern void mips3_FlushICache __P((vaddr_t addr, vaddr_t len));
extern void mips3_ForceCacheUpdate __P((void));
extern void mips3_HitFlushDCache __P((vaddr_t, int));
@@ -98,12 +95,18 @@
extern void mips3_SetWIRED __P((int));
+extern void mips5200_FlushCache __P((void));
+extern void mips5200_FlushDCache __P((vaddr_t addr, vaddr_t len));
+extern void mips5200_HitFlushDCache __P((vaddr_t, int));
+extern void mips5200_FlushICache __P((vaddr_t addr, vaddr_t len));
+
extern u_int32_t mips3_cycle_count __P((void));
extern u_int32_t mips3_write_count __P((u_int32_t));
extern u_int32_t mips3_read_compare __P((void));
extern u_int32_t mips3_read_config __P((void));
extern void mips3_write_compare __P((u_int32_t));
extern void mips3_write_xcontext_upper __P((u_int32_t));
+extern void mips3_clearBEV __P((void));
/*
* A vector with an entry for each mips-ISA-level dependent
@@ -144,17 +147,23 @@
extern mips_locore_jumpvec_t r4000_locore_vec;
#if defined(MIPS3) && !defined (MIPS1)
+#if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_5200)
+#define MachFlushCache mips5200_FlushCache
+#define MachFlushDCache mips5200_FlushDCache
+#define MachHitFlushDCache mips5200_HitFlushDCache
+#define MachFlushICache mips5200_FlushICache
+#else
#define MachFlushCache mips3_FlushCache
#if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100)
#define MachFlushDCache mips3_FlushDCache /* VR4100 */
-#elif defined(MIPS3_L2CACHE_ABSENT) && !defined(MIPS3_L2CACHE_PRESENT)
-#define MachFlushDCache mips52xx_FlushDCache /* RM5200 */
#elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT)
#define MachFlushDCache mips3_FlushDCache
#else
#define MachFlushDCache (*(mips_locore_jumpvec.flushDCache))
#endif
+#define MachHitFlushDCache mips3_HitFlushDCache
#define MachFlushICache mips3_FlushICache
+#endif
#define MachForceCacheUpdate mips3_ForceCacheUpdate
#define MachSetPID mips3_SetPID
#define MachTLBFlush() mips3_TLBFlush(mips_num_tlb_entries)
diff -r bacd943e302f -r 76b986b4b136 sys/arch/mips/mips/locore_mips3.S
--- a/sys/arch/mips/mips/locore_mips3.S Sun Mar 19 19:14:42 2000 +0000
+++ b/sys/arch/mips/mips/locore_mips3.S Sun Mar 19 19:16:13 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore_mips3.S,v 1.17 2000/02/19 01:56:21 mycroft Exp $ */
+/* $NetBSD: locore_mips3.S,v 1.18 2000/03/19 19:16:13 soren Exp $ */
/*
* Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -84,12 +84,14 @@
*
* @(#)locore.s 8.5 (Berkeley) 1/4/94
*/
-#include <machine/cdefs.h>
-#include <machine/endian.h>
+#include "opt_ddb.h"
+
+#include <sys/cdefs.h>
+
#include <mips/asm.h>
#include <mips/cpuregs.h>
#include <machine/param.h>
-#include "opt_ddb.h"
+#include <machine/endian.h>
#include "assym.h"
@@ -1689,7 +1691,6 @@
bne t0, t1, 1b
addu t0, t0, 128
-#if 1
lw t2, mips_L2CacheSize
beq t2, zero, 2f
nop
@@ -1704,8 +1705,6 @@
bne t0, t1, 1b
addu t0, t0, 128
2:
-#endif
-
j ra
nop
END(mips3_FlushCache)
@@ -1750,7 +1749,6 @@
nop
END(mips3_FlushICache)
-#if 1
/*----------------------------------------------------------------------------
*
* mips3_FlushDCache --
@@ -1796,7 +1794,6 @@
bne a1, zero, 1b
addu a0, 128
-#if 1
lw a2, mips_L2CacheSize
beq a2, zero, 2f # no secondary cache
addiu a2, -1
@@ -1812,82 +1809,10 @@
bne t1, zero, 1b
addu a0, 128
2:
-#endif
j ra
nop
END(mips3_FlushDCache)
-#endif
-
-/*----------------------------------------------------------------------------
- *
- * mips52xx_FlushDCache --
- *
- * void mips52xx_FlushDCache(paddr_t addr, len)
- *
- * Flush data cache for index range of addr to addr + len - 1.
- * The address is reduced to a kseg0 index.
- *
- * Results:
- * None.
- *
- * Side effects:
- * The contents of the cache is written back to primary memory.
- * The cache line is invalidated.
- *
- *----------------------------------------------------------------------------
- */
-LEAF(mips52xx_FlushDCache)
- lw a2, mips_L1DCacheSize
- srl a3, a2, 1 # Two way set associative cache
- addiu a2, a3, -1
- move t0, a0 # copy start address
- and a0, a0, a2 # get index into primary cache
- addu a1, 127 # Align
- li a2, 0x80000000
- addu a0, a0, a2
- addu a1, a1, a0
- and a0, a0, -128
- addu a3, a0, a3 # second set of two way cache
- subu a1, a1, a0
- srl a1, a1, 7 # Compute number of cache lines
- move t1, a1 # copy length
-1:
- cache 1, 0(a0)
- cache 1, 0(a3) # Two way set-associative cache
- cache 1, 32(a0)
- cache 1, 32(a3)
- cache 1, 64(a0)
- cache 1, 64(a3)
- cache 1, 96(a0)
- cache 1, 96(a3)
- addu a1, -1
- addu a3, 128
- bne a1, zero, 1b
- addu a0, 128
-
-#if 0
- lw a2, mips_L2CacheSize
- beq a2, zero, 2f # no secondary cache
- addiu a2, -1
- and t0,t0,a2 # secondary cache index
- li a0, 0x80000000
- addu a0, a0, t0 # reduce to kseg0 address
-1:
- cache 3, 0(a0)
- cache 3, 32(a0)
- cache 3, 64(a0)
- cache 3, 96(a0)
- addu t1, -1
- bne t1, zero, 1b
- addu a0, 128
-2:
-#endif
-
- j ra
- nop
-END(mips52xx_FlushDCache)
-
/*----------------------------------------------------------------------------
*
@@ -1972,6 +1897,271 @@
/*----------------------------------------------------------------------------
*
+ * QED R52xx cache flushing code.
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#define C_ICACHE 0
+#define C_DCACHE 1
+
+#define C_IINV (0 << 2)
+#define C_IWBINV (0 << 2)
+#define C_HINV (4 << 2)
+#define C_HWBINV (5 << 2)
+#define C_HWB (6 << 2)
+
+/*----------------------------------------------------------------------------
+ *
+ * mips5200_FlushCache -- (QED)
+ *
+ * Flush the caches. Assumes a line size of 32 bytes for speed.
+ * Does not currently support a second level cache.
+ *
+ * Results:
+ * None.
+ *
+ * Side effects:
+ * The contents of the caches is flushed.
+ *
+ *----------------------------------------------------------------------------
+ */
+LEAF(mips5200_FlushCache)
+ lw t1, mips_L1ICacheSize
+ lw t2, mips_L1DCacheSize
+
+ /*
+ * Flush the instruction cache.
+ */
+ li t0, MIPS_KSEG0_START
+ srl t1, 1 # Two way set assoc
+ or t3, t1, t0 # Second way address
+ addu t1, t0, t1 # End address
+1:
+ cache C_ICACHE|C_IINV, 0(t0)
+ cache C_ICACHE|C_IINV, 0(t3)
+ cache C_ICACHE|C_IINV, 32(t0)
+ cache C_ICACHE|C_IINV, 32(t3)
+ cache C_ICACHE|C_IINV, 64(t0)
+ cache C_ICACHE|C_IINV, 64(t3)
+ cache C_ICACHE|C_IINV, 96(t0)
+ addu t0, t0, 128
+ cache C_ICACHE|C_IINV, 96(t3)
+ bne t0, t1, 1b
+ addu t3, t3, 128 # Branch delay slot
+
+ /*
+ * Flush the data cache.
+ */
+ li t0, MIPS_KSEG0_START
+ srl t2, 1 # Two way set assoc
+ or t3, t2, t0 # Second way address
+ addu t1, t0, t2 # End address
+1:
+ cache C_DCACHE|C_IWBINV, 0(t0)
+ cache C_DCACHE|C_IWBINV, 0(t3)
+ cache C_DCACHE|C_IWBINV, 32(t0)
+ cache C_DCACHE|C_IWBINV, 32(t3)
+ cache C_DCACHE|C_IWBINV, 64(t0)
+ cache C_DCACHE|C_IWBINV, 64(t3)
+ cache C_DCACHE|C_IWBINV, 96(t0)
+ addu t0, t0, 128
+ cache C_DCACHE|C_IWBINV, 96(t3)
+ bne t0, t1, 1b
+ addu t3, t3, 128 # Branch delay slot
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