[src/trunk]: src/sys/arch/mips/mips Mark the Au1x00 CPUs as having a fully co...

[simonb <simonb%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/7bd3f6ccdd49
branches:  trunk
changeset: 540511:7bd3f6ccdd49
user:      simonb <simonb%NetBSD.org@localhost>
date:      Tue Dec 17 12:07:50 2002 +0000

description:
Mark the Au1x00 CPUs as having a fully coherent data cache that doesn't
require flushing (even in the instruction cache handlers).  This gives
about a 4% improvement in a "make depend" benchmark.

Mark the SB-1 CPUs as having a fully coherent data cache that only
require flushing in the instruction cache handlers.  This gives about
a 5% improvement in a "make depend" benchmark.

diffstat:

 sys/arch/mips/mips/mips_machdep.c |  29 ++++++++++++++++++-----------
 1 files changed, 18 insertions(+), 11 deletions(-)

diffs (61 lines):

diff -r 40ed8490bf9e -r 7bd3f6ccdd49 sys/arch/mips/mips/mips_machdep.c
--- a/sys/arch/mips/mips/mips_machdep.c Tue Dec 17 12:04:29 2002 +0000
+++ b/sys/arch/mips/mips/mips_machdep.c Tue Dec 17 12:07:50 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: mips_machdep.c,v 1.155 2002/11/15 01:16:18 simonb Exp $        */
+/*     $NetBSD: mips_machdep.c,v 1.156 2002/12/17 12:07:50 simonb Exp $        */
 
 /*
  * Copyright 2002 Wasabi Systems, Inc.
@@ -120,7 +120,7 @@
 
 #include <sys/cdefs.h>                 /* RCS ID & Copyright macro defns */
 
-__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.155 2002/11/15 01:16:18 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.156 2002/12/17 12:07:50 simonb Exp $");
 
 #include "opt_cputype.h"
 
@@ -380,26 +380,33 @@
          MIPS64_FLAGS,                         "20Kc"                  },
 
        { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1000, -1, 0,
-         MIPS32_FLAGS | CPU_MIPS_NO_WAIT,      "Au1000 (Rev 1 core)"   },
+         MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
+                                               "Au1000 (Rev 1 core)"   },
        { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1000, -1, 0,
-         MIPS32_FLAGS | CPU_MIPS_NO_WAIT,      "Au1000 (Rev 2 core)"   },
+         MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
+                                               "Au1000 (Rev 2 core)"   },
 
        { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1500, -1, 0,
-         MIPS32_FLAGS | CPU_MIPS_NO_WAIT,      "Au1500 (Rev 1 core)"   },
+         MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
+                                               "Au1500 (Rev 1 core)"   },
        { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1500, -1, 0,
-         MIPS32_FLAGS | CPU_MIPS_NO_WAIT,      "Au1500 (Rev 2 core)"   },
+         MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
+                                               "Au1500 (Rev 2 core)"   },
 
        { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1100, -1, 0,
-         MIPS32_FLAGS | CPU_MIPS_NO_WAIT,      "Au1100 (Rev 1 core)"   },
+         MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
+                                               "Au1100 (Rev 1 core)"   },
        { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1100, -1, 0,
-         MIPS32_FLAGS | CPU_MIPS_NO_WAIT,      "Au1100 (Rev 2 core)"   },
+         MIPS32_FLAGS | CPU_MIPS_NO_WAIT | CPU_MIPS_I_D_CACHE_COHERENT,
+                                               "Au1100 (Rev 2 core)"   },
 
        /* The SB1 CPUs use a CCA of 5 - "Cacheable Coherent Shareable" */
        { MIPS_PRID_CID_SIBYTE, MIPS_SB1, -1,   -1, -1, 0,
-         MIPS64_FLAGS | CPU_MIPS_HAVE_SPECIAL_CCA | \
-         (5 << CPU_MIPS_CACHED_CCA_SHIFT),     "SB1"                   },
+         MIPS64_FLAGS | CPU_MIPS_D_CACHE_COHERENT |
+         CPU_MIPS_HAVE_SPECIAL_CCA | (5 << CPU_MIPS_CACHED_CCA_SHIFT),
+                                               "SB1"                   },
 
-       { 0, 0, 0,                              0, 0, 64,
+       { 0, 0, 0,                              0, 0, 0,
          0,                                    NULL                    }
 };