[src/netbsd-1-6]: src/sys/arch/powerpc/mpc6xx Pull up revisions 1-15-1.19 (re...

[lukem <lukem%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/ee271d3764ea
branches:  netbsd-1-6
changeset: 528012:ee271d3764ea
user:      lukem <lukem%NetBSD.org@localhost>
date:      Thu Jun 20 02:52:11 2002 +0000

description:
Pull up revisions 1-15-1.19 (requested by wrstuden in ticket #322):
    revision 1.19
        Fix recent bugs seen on Performa 4400 macppc's by
        Makoto Fujiwara <makoto%ki.nu@localhost> and Manuel Bouyer <bouyer%netbsd.org@localhost>.
        Help from Allen Briggs, Jason Thorpe, and Matt Thomas.
        We need to call cpu_cache_probe() early in boot (machdep.c).
        Add 603 info for completeness, and use NBPG not PAGESIZE, as the
        latter relies on uvm being setup (cpu_subr.c).
        Let uvm_page_recolor() be called before uvm has been set up; just
        note the page coloring value (uvm_page.c).

    revision 1.18
        Add a missing return; after print the 745x cache size(s).

    revision 1.17
        Add a case label for the 603ev cache (identical to 603e).

    revision 1.16
        Cosmetics: there are exceptions to the PVR major/minor rule.

    revision 1.15
        Fill in real cache size/organization information and recolor; currently
        doesn't make a difference except for the 604e.
        XXX Does not consider L2 caches yet.

diffstat:

 sys/arch/powerpc/mpc6xx/cpu_subr.c |  62 ++++++++++++++++++++++++++++++++++---
 1 files changed, 56 insertions(+), 6 deletions(-)

diffs (92 lines):

diff -r bc26e56cefb4 -r ee271d3764ea sys/arch/powerpc/mpc6xx/cpu_subr.c
--- a/sys/arch/powerpc/mpc6xx/cpu_subr.c        Thu Jun 20 02:49:12 2002 +0000
+++ b/sys/arch/powerpc/mpc6xx/cpu_subr.c        Thu Jun 20 02:52:11 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpu_subr.c,v 1.14 2002/04/03 00:09:52 matt Exp $       */
+/*     $NetBSD: cpu_subr.c,v 1.14.4.1 2002/06/20 02:52:11 lukem Exp $  */
 
 /*-
  * Copyright (c) 2001 Matt Thomas.
@@ -72,11 +72,53 @@
 void
 cpu_probe_cache(void)
 {
-       /* XXXX Initialze cache_info */
-       curcpu()->ci_ci.dcache_size = PAGE_SIZE;
+       u_int assoc, pvr, vers;
+
+       __asm __volatile ("mfpvr %0" : "=r"(pvr));
+       vers = pvr >> 16;
+
+       switch (vers) {
+#define        K       *1024
+       case MPC601:
+       case MPC750:
+       case MPC7450:
+       case MPC7455:
+               curcpu()->ci_ci.dcache_size = 32 K;
+               curcpu()->ci_ci.icache_size = 32 K;
+               assoc = 8;
+               break;
+       case MPC603:
+               curcpu()->ci_ci.dcache_size = 8 K;
+               curcpu()->ci_ci.icache_size = 8 K;
+               assoc = 2;
+               break;
+       case MPC603e:
+       case MPC603ev:
+       case MPC604:
+               curcpu()->ci_ci.dcache_size = 16 K;
+               curcpu()->ci_ci.icache_size = 16 K;
+               assoc = 4;
+               break;
+       case MPC604ev:
+               curcpu()->ci_ci.dcache_size = 32 K;
+               curcpu()->ci_ci.icache_size = 32 K;
+               assoc = 4;
+               break;
+       default:
+               curcpu()->ci_ci.dcache_size = NBPG;
+               curcpu()->ci_ci.icache_size = NBPG;
+               assoc = 1;
+#undef K
+       }
+
+       /* Presently common across all implementations. */
        curcpu()->ci_ci.dcache_line_size = CACHELINESIZE;
-       curcpu()->ci_ci.icache_size = PAGE_SIZE;
        curcpu()->ci_ci.icache_line_size = CACHELINESIZE;
+
+       /*
+        * Possibly recolor.
+        */
+        uvm_page_recolor(atop(curcpu()->ci_ci.dcache_line_size / assoc));
 }
 
 struct cpu_info *
@@ -311,8 +353,15 @@
 
        asm ("mfpvr %0" : "=r"(pvr));
        vers = pvr >> 16;
-       maj = (pvr >>  8) & 0xff;
-       min = (pvr >>  0) & 0xff;
+       switch (vers) {
+       case MPC7410:
+               min = (pvr >> 0) & 0xff;
+               maj = min <= 4 ? 1 : 2;
+               break;
+       default:
+               maj = (pvr >>  8) & 0xff;
+               min = (pvr >>  0) & 0xff;
+       }
 
        for (cp = models; cp->name != NULL; cp++) {
                if (cp->version == vers)
@@ -380,6 +429,7 @@
                                printf(", %cMB L3 backside cache",
                                   l3cr & L3CR_L3SIZ ? '2' : '1');
                        printf("\n");
+                       return;
                }
                switch (l2cr & L2CR_L2SIZ) {
                case L2SIZ_256K: