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[src/trunk]: src/sys/arch/macppc/macppc Inline some functions.
details: https://anonhg.NetBSD.org/src/rev/ec2016bc5767
branches: trunk
changeset: 476167:ec2016bc5767
user: tsubai <tsubai%NetBSD.org@localhost>
date: Wed Sep 08 17:28:02 1999 +0000
description:
Inline some functions.
diffstat:
sys/arch/macppc/macppc/extintr.c | 195 +++++++++++++++++++-------------------
1 files changed, 99 insertions(+), 96 deletions(-)
diffs (228 lines):
diff -r cfc01c58c8d7 -r ec2016bc5767 sys/arch/macppc/macppc/extintr.c
--- a/sys/arch/macppc/macppc/extintr.c Wed Sep 08 16:52:08 1999 +0000
+++ b/sys/arch/macppc/macppc/extintr.c Wed Sep 08 17:28:02 1999 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: extintr.c,v 1.8 1999/03/24 05:51:04 mrg Exp $ */
+/* $NetBSD: extintr.c,v 1.9 1999/09/08 17:28:02 tsubai Exp $ */
/*-
* Copyright (c) 1995 Per Fogelstrom
@@ -64,9 +64,9 @@
extern u_int *heathrow_FCR;
static __inline int cntlzw __P((int));
-static int read_irq __P((void));
+static __inline int read_irq __P((void));
+static __inline int mapirq __P((int));
static void enable_irq __P((int));
-static int mapirq __P((int));
static int hwirq[ICU_LEN], virq[64];
static int virq_max = 0;
@@ -84,6 +84,102 @@
#define INT_LEVEL_REG1 (INT_LEVEL_REG0 - 0x10)
/*
+ * Map 64 irqs into 32 (bits).
+ */
+int
+mapirq(irq)
+ int irq;
+{
+ int v;
+
+ if (irq < 0 || irq >= 64)
+ panic("invalid irq");
+ if (virq[irq])
+ return virq[irq];
+
+ virq_max++;
+ v = virq_max;
+ if (v > HWIRQ_MAX)
+ panic("virq overflow");
+
+ hwirq[v] = irq;
+ virq[irq] = v;
+
+ return v;
+}
+
+/*
+ * Count leading zeros.
+ */
+static __inline int
+cntlzw(x)
+ int x;
+{
+ int a;
+
+ __asm __volatile ("cntlzw %0,%1" : "=r"(a) : "r"(x));
+
+ return a;
+}
+
+int
+read_irq()
+{
+ int rv = 0;
+ int state0, state1, p;
+
+ state0 = in32rb(INT_STATE_REG0);
+ if (state0)
+ out32rb(INT_CLEAR_REG0, state0);
+ while (state0) {
+ p = 31 - cntlzw(state0);
+ rv |= 1 << virq[p];
+ state0 &= ~(1 << p);
+ }
+
+ if (heathrow_FCR) /* has heathrow? */
+ state1 = in32rb(INT_STATE_REG1);
+ else
+ state1 = 0;
+
+ if (state1)
+ out32rb(INT_CLEAR_REG1, state1);
+ while (state1) {
+ p = 31 - cntlzw(state1);
+ rv |= 1 << virq[p + 32];
+ state1 &= ~(1 << p);
+ }
+
+ /* 1 << 0 is invalid. */
+ return rv & ~1;
+}
+
+void
+enable_irq(x)
+ int x;
+{
+ int state0, state1, v;
+ int irq;
+
+ x &= HWIRQ_MASK; /* XXX Higher bits are software interrupts. */
+
+ state0 = state1 = 0;
+ while (x) {
+ v = 31 - cntlzw(x);
+ irq = hwirq[v];
+ if (irq < 32)
+ state0 |= 1 << irq;
+ else
+ state1 |= 1 << (irq - 32);
+ x &= ~(1 << v);
+ }
+
+ out32rb(INT_ENABLE_REG0, state0);
+ if (heathrow_FCR)
+ out32rb(INT_ENABLE_REG1, state1);
+}
+
+/*
* Recalculate the interrupt masks from scratch.
* We could code special registry and deregistry versions of this function that
* would be faster, but the code would be nastier, and we don't expect this to
@@ -324,20 +420,6 @@
}
/*
- * Count leading zeros.
- */
-static __inline int
-cntlzw(x)
- int x;
-{
- int a;
-
- __asm __volatile ("cntlzw %0,%1" : "=r"(a) : "r"(x));
-
- return a;
-}
-
-/*
* external interrupt handler
*/
void
@@ -440,82 +522,3 @@
asm volatile("mtmsr %0" :: "r"(emsr));
processing = 0;
}
-
-/*
- * Map 64 irqs into 32 (bits).
- */
-int
-mapirq(irq)
- int irq;
-{
- int v;
-
- if (irq < 0 || irq >= 64)
- panic("invalid irq");
- virq_max++;
- v = virq_max;
- if (v > HWIRQ_MAX)
- panic("virq overflow");
-
- hwirq[v] = irq;
- virq[irq] = v;
-
- return v;
-}
-
-int
-read_irq()
-{
- int rv = 0;
- int state0, state1, p;
-
- state0 = in32rb(INT_STATE_REG0);
- if (state0)
- out32rb(INT_CLEAR_REG0, state0);
- while (state0) {
- p = 31 - cntlzw(state0);
- rv |= 1 << virq[p];
- state0 &= ~(1 << p);
- }
-
- if (heathrow_FCR) /* has heathrow? */
- state1 = in32rb(INT_STATE_REG1);
- else
- state1 = 0;
-
- if (state1)
- out32rb(INT_CLEAR_REG1, state1);
- while (state1) {
- p = 31 - cntlzw(state1);
- rv |= 1 << virq[p + 32];
- state1 &= ~(1 << p);
- }
-
- /* 1 << 0 is invalid. */
- return rv & ~1;
-}
-
-void
-enable_irq(x)
- int x;
-{
- int state0, state1, v;
- int irq;
-
- x &= HWIRQ_MASK; /* XXX Higher bits are software interrupts. */
-
- state0 = state1 = 0;
- while (x) {
- v = 31 - cntlzw(x);
- irq = hwirq[v];
- if (irq < 32)
- state0 |= 1 << irq;
- else
- state1 |= 1 << (irq - 32);
- x &= ~(1 << v);
- }
-
- out32rb(INT_ENABLE_REG0, state0);
- if (heathrow_FCR)
- out32rb(INT_ENABLE_REG1, state1);
-}
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