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[src/trunk]: src/sys/arch/mips cache_r10k.c rev. 1.1 is broken. Because,
details: https://anonhg.NetBSD.org/src/rev/64fcb3f9fa56
branches: trunk
changeset: 554707:64fcb3f9fa56
user: shin <shin%NetBSD.org@localhost>
date: Sat Nov 01 04:42:56 2003 +0000
description:
cache_r10k.c rev. 1.1 is broken. Because,
1) R10k uses VA0 to select cache ways, but in rev. 1.1, VA14
is used instead.
2) R10k does not support HitWriteBack and should map HitWriteBack
to HitWriteBackInvalidate, but in rev. 1.1, HitWriteBack is not
handled properly.
So, cache_r10k.c rev. 1.1 was replaced by new implementation.
diffstat:
sys/arch/mips/include/cache_r10k.h | 101 ++--------------
sys/arch/mips/mips/cache.c | 114 +++++-------------
sys/arch/mips/mips/cache_r10k.c | 226 ++++++++++++++++++++++++++++++------
3 files changed, 229 insertions(+), 212 deletions(-)
diffs (truncated from 562 to 300 lines):
diff -r 3e43be11d62d -r 64fcb3f9fa56 sys/arch/mips/include/cache_r10k.h
--- a/sys/arch/mips/include/cache_r10k.h Sat Nov 01 03:45:58 2003 +0000
+++ b/sys/arch/mips/include/cache_r10k.h Sat Nov 01 04:42:56 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cache_r10k.h,v 1.1 2003/10/05 11:10:25 tsutsui Exp $ */
+/* $NetBSD: cache_r10k.h,v 1.2 2003/11/01 04:42:56 shin Exp $ */
/*
* Copyright (c) 2003 KIYOHARA Takashi <kiyohara%kk.iij4u.or.jp@localhost>
@@ -69,94 +69,19 @@
#if defined(_KERNEL) && !defined(_LOCORE)
-/*
- * cache_r10k_op_8lines_64:
- *
- * Perform the specified cache operation on 8 64-byte cache lines.
- */
-#define cache_r10k_op_8lines_64(va, op) \
-do { \
- __asm __volatile( \
- ".set noreorder \n\t" \
- "cache %1, 0x000(%0); cache %1, 0x040(%0) \n\t" \
- "cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n\t" \
- "cache %1, 0x100(%0); cache %1, 0x140(%0) \n\t" \
- "cache %1, 0x180(%0); cache %1, 0x1c0(%0) \n\t" \
- ".set reorder" \
- : \
- : "r" (va), "i" (op) \
- : "memory"); \
-} while (/*CONSTCOND*/0)
-
-/*
- * cache_r10k_op_32lines_64:
- *
- * Perform the specified cache operation on 32 64-byte
- * cache lines.
- */
-#define cache_r10k_op_32lines_64(va, op) \
-do { \
- __asm __volatile( \
- ".set noreorder \n\t" \
- "cache %1, 0x000(%0); cache %1, 0x040(%0); \n\t" \
- "cache %1, 0x080(%0); cache %1, 0x0c0(%0); \n\t" \
- "cache %1, 0x100(%0); cache %1, 0x140(%0); \n\t" \
- "cache %1, 0x180(%0); cache %1, 0x1c0(%0); \n\t" \
- "cache %1, 0x200(%0); cache %1, 0x240(%0); \n\t" \
- "cache %1, 0x280(%0); cache %1, 0x2c0(%0); \n\t" \
- "cache %1, 0x300(%0); cache %1, 0x340(%0); \n\t" \
- "cache %1, 0x380(%0); cache %1, 0x3c0(%0); \n\t" \
- "cache %1, 0x400(%0); cache %1, 0x440(%0); \n\t" \
- "cache %1, 0x480(%0); cache %1, 0x4c0(%0); \n\t" \
- "cache %1, 0x500(%0); cache %1, 0x540(%0); \n\t" \
- "cache %1, 0x580(%0); cache %1, 0x5c0(%0); \n\t" \
- "cache %1, 0x600(%0); cache %1, 0x640(%0); \n\t" \
- "cache %1, 0x680(%0); cache %1, 0x6c0(%0); \n\t" \
- "cache %1, 0x700(%0); cache %1, 0x740(%0); \n\t" \
- "cache %1, 0x780(%0); cache %1, 0x7c0(%0); \n\t" \
- ".set reorder" \
- : \
- : "r" (va), "i" (op) \
- : "memory"); \
-} while (/*CONSTCOND*/0)
-
-/*
- * cache_r10k_op_16lines_32_2way:
- *
- * Perform the specified cache operation on 16 64-byte
- * cache lines, 2-ways.
- */
-#define cache_r10k_op_16lines_64_2way(va1, va2, op) \
-do { \
- __asm __volatile( \
- ".set noreorder \n\t" \
- "cache %2, 0x000(%0); cache %2, 0x000(%1); \n\t" \
- "cache %2, 0x040(%0); cache %2, 0x040(%1); \n\t" \
- "cache %2, 0x080(%0); cache %2, 0x080(%1); \n\t" \
- "cache %2, 0x0c0(%0); cache %2, 0x0c0(%1); \n\t" \
- "cache %2, 0x100(%0); cache %2, 0x100(%1); \n\t" \
- "cache %2, 0x140(%0); cache %2, 0x140(%1); \n\t" \
- "cache %2, 0x180(%0); cache %2, 0x180(%1); \n\t" \
- "cache %2, 0x1c0(%0); cache %2, 0x1c0(%1); \n\t" \
- "cache %2, 0x200(%0); cache %2, 0x200(%1); \n\t" \
- "cache %2, 0x240(%0); cache %2, 0x240(%1); \n\t" \
- "cache %2, 0x280(%0); cache %2, 0x280(%1); \n\t" \
- "cache %2, 0x2c0(%0); cache %2, 0x2c0(%1); \n\t" \
- "cache %2, 0x300(%0); cache %2, 0x300(%1); \n\t" \
- "cache %2, 0x340(%0); cache %2, 0x340(%1); \n\t" \
- "cache %2, 0x380(%0); cache %2, 0x380(%1); \n\t" \
- "cache %2, 0x3c0(%0); cache %2, 0x3c0(%1); \n\t" \
- ".set reorder" \
- : \
- : "r" (va1), "r" (va2), "i" (op) \
- : "memory"); \
-} while (/*CONSTCOND*/0)
-
-void r10k_icache_sync_all_64(void);
-void r10k_icache_sync_range_64(vaddr_t, vsize_t);
-void r10k_icache_sync_range_index_64(vaddr_t, vsize_t);
-
+void r10k_icache_sync_all(void);
+void r10k_icache_sync_range(vaddr_t, vsize_t);
+void r10k_icache_sync_range_index(vaddr_t, vsize_t);
+void r10k_pdcache_wbinv_all(void);
+void r10k_pdcache_wbinv_range(vaddr_t, vsize_t);
+void r10k_pdcache_wbinv_range_index(vaddr_t, vsize_t);
+void r10k_pdcache_inv_range(vaddr_t, vsize_t);
void r10k_pdcache_wb_range(vaddr_t, vsize_t);
+void r10k_sdcache_wbinv_all(void);
+void r10k_sdcache_wbinv_range(vaddr_t, vsize_t);
+void r10k_sdcache_wbinv_range_index(vaddr_t, vsize_t);
+void r10k_sdcache_inv_range(vaddr_t, vsize_t);
+void r10k_sdcache_wb_range(vaddr_t, vsize_t);
#endif /* _KERNEL && !_LOCORE */
diff -r 3e43be11d62d -r 64fcb3f9fa56 sys/arch/mips/mips/cache.c
--- a/sys/arch/mips/mips/cache.c Sat Nov 01 03:45:58 2003 +0000
+++ b/sys/arch/mips/mips/cache.c Sat Nov 01 04:42:56 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cache.c,v 1.22 2003/10/11 09:09:15 tsutsui Exp $ */
+/* $NetBSD: cache.c,v 1.23 2003/11/01 04:42:56 shin Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -68,7 +68,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.22 2003/10/11 09:09:15 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.23 2003/11/01 04:42:56 shin Exp $");
#include "opt_cputype.h"
#include "opt_mips_cache.h"
@@ -609,45 +609,30 @@
#endif /* MIPS3_5900 */
#ifdef ENABLE_MIPS4_CACHE_R10K
case MIPS_R10000:
- /* cache spec */
+ case MIPS_R12000:
+ case MIPS_R14000:
mips_picache_ways = 2;
mips_pdcache_ways = 2;
mips_sdcache_ways = 2;
mips4_get_cache_config(csizebase);
- switch (mips_picache_line_size) {
- case 64: /* 64 Byte */
- mips_cache_ops.mco_icache_sync_all =
- r10k_icache_sync_all_64;
- mips_cache_ops.mco_icache_sync_range =
- r10k_icache_sync_range_64;
- mips_cache_ops.mco_icache_sync_range_index =
- r10k_icache_sync_range_index_64;
- break;
-
- default:
- panic("r10k picache line size %d",
- mips_picache_line_size);
- }
- switch (mips_pdcache_line_size) {
- case 32: /* 32 Byte */
- mips_cache_ops.mco_pdcache_wbinv_all =
- r5k_pdcache_wbinv_all_32;
- mips_cache_ops.mco_pdcache_wbinv_range =
- r5k_pdcache_wbinv_range_32;
- mips_cache_ops.mco_pdcache_wbinv_range_index =
- r5k_pdcache_wbinv_range_index_32;
- mips_cache_ops.mco_pdcache_inv_range =
- r5k_pdcache_inv_range_32;
- mips_cache_ops.mco_pdcache_wb_range =
- r10k_pdcache_wb_range;
- break;
-
- default:
- panic("r10k pdcache line size %d",
- mips_pdcache_line_size);
- }
+ mips_cache_ops.mco_icache_sync_all =
+ r10k_icache_sync_all;
+ mips_cache_ops.mco_icache_sync_range =
+ r10k_icache_sync_range;
+ mips_cache_ops.mco_icache_sync_range_index =
+ r10k_icache_sync_range_index;
+ mips_cache_ops.mco_pdcache_wbinv_all =
+ r10k_pdcache_wbinv_all;
+ mips_cache_ops.mco_pdcache_wbinv_range =
+ r10k_pdcache_wbinv_range;
+ mips_cache_ops.mco_pdcache_wbinv_range_index =
+ r10k_pdcache_wbinv_range_index;
+ mips_cache_ops.mco_pdcache_inv_range =
+ r10k_pdcache_inv_range;
+ mips_cache_ops.mco_pdcache_wb_range =
+ r10k_pdcache_wb_range;
break;
#endif /* ENABLE_MIPS4_CACHE_R10K */
#endif /* MIPS3 || MIPS4 */
@@ -768,53 +753,18 @@
break;
#ifdef ENABLE_MIPS4_CACHE_R10K
case MIPS_R10000:
- switch (mips_sdcache_ways) {
- case 2:
- switch (mips_sdcache_line_size) {
- case 64:
- mips_cache_ops.mco_sdcache_wbinv_all =
- r4k_sdcache_wbinv_all_generic;
- mips_cache_ops.mco_sdcache_wbinv_range =
- r4k_sdcache_wbinv_range_generic;
- mips_cache_ops.mco_sdcache_wbinv_range_index =
- r4k_sdcache_wbinv_range_index_generic;
- mips_cache_ops.mco_sdcache_inv_range =
- r4k_sdcache_inv_range_generic;
- mips_cache_ops.mco_sdcache_wb_range =
-#if 0 /* XXX needs real wb functions for r10k 2way L2 cache */
- r4k_sdcache_wb_range_generic;
-#else
- r4k_sdcache_wbinv_range_generic;
-#endif
- break;
-
- case 128:
- mips_cache_ops.mco_sdcache_wbinv_all =
- r4k_sdcache_wbinv_all_128;
- mips_cache_ops.mco_sdcache_wbinv_range =
- r4k_sdcache_wbinv_range_128;
- mips_cache_ops.mco_sdcache_wbinv_range_index =
- r4k_sdcache_wbinv_range_index_128;
- mips_cache_ops.mco_sdcache_inv_range =
- r4k_sdcache_inv_range_128;
- mips_cache_ops.mco_sdcache_wb_range =
-#if 0 /* XXX needs real wb functions for r10k 2way L2 cache */
- r4k_sdcache_wb_range_128;
-#else
- r4k_sdcache_wbinv_range_128;
-#endif
- break;
-
- default:
- panic("r10k sdcache %d way line size %d",
- mips_sdcache_ways, mips_sdcache_line_size);
- }
- break;
-
- default:
- panic("r10k sdcache %d way line size %d",
- mips_sdcache_ways, mips_sdcache_line_size);
- }
+ case MIPS_R12000:
+ case MIPS_R14000:
+ mips_cache_ops.mco_sdcache_wbinv_all =
+ r10k_sdcache_wbinv_all;
+ mips_cache_ops.mco_sdcache_wbinv_range =
+ r10k_sdcache_wbinv_range;
+ mips_cache_ops.mco_sdcache_wbinv_range_index =
+ r10k_sdcache_wbinv_range_index;
+ mips_cache_ops.mco_sdcache_inv_range =
+ r10k_sdcache_inv_range;
+ mips_cache_ops.mco_sdcache_wb_range =
+ r10k_sdcache_wb_range;
break;
#endif /* ENABLE_MIPS4_CACHE_R10K */
#endif /* MIPS3 || MIPS4 */
diff -r 3e43be11d62d -r 64fcb3f9fa56 sys/arch/mips/mips/cache_r10k.c
--- a/sys/arch/mips/mips/cache_r10k.c Sat Nov 01 03:45:58 2003 +0000
+++ b/sys/arch/mips/mips/cache_r10k.c Sat Nov 01 04:42:56 2003 +0000
@@ -1,7 +1,7 @@
-/* $NetBSD: cache_r10k.c,v 1.1 2003/10/05 11:10:25 tsutsui Exp $ */
+/* $NetBSD: cache_r10k.c,v 1.2 2003/11/01 04:42:56 shin Exp $ */
-/*
- * Copyright (c) 2003 KIYOHARA Takashi <kiyohara%kk.iij4u.or.jp@localhost>
+/*-
+ * Copyright (c) 2003 Takao Shinohara.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -59,53 +59,44 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include <sys/cdefs.h>
-
#include <sys/param.h>
#include <mips/cache.h>
#include <mips/cache_r4k.h>
-#include <mips/cache_r5k.h>
#include <mips/cache_r10k.h>
-#include <mips/locore.h>
/*
* Cache operations for R10000-style caches:
*
- * - 2-way set-associative
- * - Write-back
- * - Virtually indexed, physically tagged
- *
+ * 2-way, write-back
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