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[src/nathanw_sa]: src/sys/arch/arm/arm32 Fix cpu_switch() after RAS integrati...
details: https://anonhg.NetBSD.org/src/rev/b09a5c693769
branches: nathanw_sa
changeset: 506236:b09a5c693769
user: thorpej <thorpej%NetBSD.org@localhost>
date: Wed Sep 18 23:57:32 2002 +0000
description:
Fix cpu_switch() after RAS integration from trunk.
diffstat:
sys/arch/arm/arm32/cpuswitch.S | 20 ++++++++++++--------
1 files changed, 12 insertions(+), 8 deletions(-)
diffs (53 lines):
diff -r 4d712891da93 -r b09a5c693769 sys/arch/arm/arm32/cpuswitch.S
--- a/sys/arch/arm/arm32/cpuswitch.S Tue Sep 17 23:50:18 2002 +0000
+++ b/sys/arch/arm/arm32/cpuswitch.S Wed Sep 18 23:57:32 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpuswitch.S,v 1.3.2.23 2002/09/17 23:50:18 nathanw Exp $ */
+/* $NetBSD: cpuswitch.S,v 1.3.2.24 2002/09/18 23:57:32 thorpej Exp $ */
/*
* Copyright (c) 1994-1998 Mark Brinicombe.
@@ -634,24 +634,29 @@
msr cpsr_c, r3 /* Restore the old mode */
/* Restore all the save registers */
- add r7, r1, #PCB_R8
+ add r7, r9, #PCB_R8
ldmia r7, {r8-r13}
- mov r7, r1 /* preserve PCB pointer */
+ sub r7, r7, #PCB_R8 /* restore PCB pointer */
+
+ ldr r5, [r6, #(L_PROC)] /* fetch the proc for below */
+
+ /* rem: r4 = return value */
+ /* rem: r5 = new lwp's proc */
+ /* rem: r6 = new lwp */
+ /* rem: r7 = new pcb */
#ifdef ARMFPE
- add r0, r9, #(USER_SIZE) & 0x00ff
+ add r0, r7, #(USER_SIZE) & 0x00ff
add r0, r0, #(USER_SIZE) & 0xff00
bl _C_LABEL(arm_fpe_core_changecontext)
#endif
/* We can enable interrupts again */
IRQenable
- /*
- * NOTE: We can now no longer use r8-r13.
- */
/* rem: r4 = return value */
+ /* rem: r5 = new lwp's proc */
/* rem: r6 = new lwp */
/* rem: r7 = new PCB */
@@ -659,7 +664,6 @@
* Check for restartable atomic sequences (RAS).
*/
- ldr r5, [r6, #(L_PROC)]
ldr r2, [r5, #(P_NRAS)]
ldr r4, [r7, #(PCB_TF)] /* r4 = trapframe (used below) */
teq r2, #0 /* p->p_nras == 0? */
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