[src/trunk]: src/sys/arch/sparc/sparc swift_cache_enable: set cache enable bi...

[pk <pk%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/5a1c9de0f008
branches:  trunk
changeset: 555023:5a1c9de0f008
user:      pk <pk%NetBSD.org@localhost>
date:      Fri Nov 07 14:50:21 2003 +0000

description:
swift_cache_enable: set cache enable bits after resetting the cache tags.

diffstat:

 sys/arch/sparc/sparc/cache.c |  8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diffs (36 lines):

diff -r e29ebdb5eafd -r 5a1c9de0f008 sys/arch/sparc/sparc/cache.c
--- a/sys/arch/sparc/sparc/cache.c      Fri Nov 07 14:50:18 2003 +0000
+++ b/sys/arch/sparc/sparc/cache.c      Fri Nov 07 14:50:21 2003 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.c,v 1.81 2003/08/24 00:41:43 mrg Exp $ */
+/*     $NetBSD: cache.c,v 1.82 2003/11/07 14:50:21 pk Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -59,7 +59,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.81 2003/08/24 00:41:43 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cache.c,v 1.82 2003/11/07 14:50:21 pk Exp $");
 
 #include "opt_multiprocessor.h"
 #include "opt_sparc_arch.h"
@@ -254,8 +254,6 @@
        cache_alias_bits = (cache_alias_dist - 1) & ~PGOFSET;
 
        pcr = lda(SRMMU_PCR, ASI_SRMMU);
-       pcr |= (SWIFT_PCR_ICE | SWIFT_PCR_DCE);
-       sta(SRMMU_PCR, ASI_SRMMU, pcr);
 
        /* Now reset cache tag memory if cache not yet enabled */
        ls = CACHEINFO.ic_linesize;
@@ -270,6 +268,8 @@
                for (i = 0; i < ts; i += ls)
                        sta(i, ASI_DCACHETAG, 0);
 
+       pcr |= (SWIFT_PCR_ICE | SWIFT_PCR_DCE);
+       sta(SRMMU_PCR, ASI_SRMMU, pcr);
        CACHEINFO.c_enabled = 1;
 }