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[src/trunk]: src/sys/arch/hpcmips/vr add VR4101 specific BCU registers.
details: https://anonhg.NetBSD.org/src/rev/5a7ad5edcd4b
branches: trunk
changeset: 508409:5a7ad5edcd4b
user: sato <sato%NetBSD.org@localhost>
date: Wed Apr 11 08:52:59 2001 +0000
description:
add VR4101 specific BCU registers.
add VR4122 specific BCU registers.
add cpu specific comments.
diffstat:
sys/arch/hpcmips/vr/bcureg.h | 333 +++++++++++++++++++++++++++++++++++++-----
1 files changed, 288 insertions(+), 45 deletions(-)
diffs (truncated from 457 to 300 lines):
diff -r b139f0c7d03a -r 5a7ad5edcd4b sys/arch/hpcmips/vr/bcureg.h
--- a/sys/arch/hpcmips/vr/bcureg.h Wed Apr 11 08:44:06 2001 +0000
+++ b/sys/arch/hpcmips/vr/bcureg.h Wed Apr 11 08:52:59 2001 +0000
@@ -1,7 +1,7 @@
-/* $NetBSD: bcureg.h,v 1.3 2000/01/27 06:25:54 sato Exp $ */
+/* $NetBSD: bcureg.h,v 1.4 2001/04/11 08:52:59 sato Exp $ */
/*-
- * Copyright (c) 1999 SATO Kazumi. All rights reserved.
+ * Copyright (c) 1999-2001 SATO Kazumi. All rights reserved.
* Copyright (c) 1999 PocketBSD Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -36,44 +36,75 @@
/*
* BCU (Bus Control Unit) Registers definitions.
- * start 0xB000000
+ * start 0xB000000 (vr4101,4102,4111,4121)
+ * start 0xA000000 (vr4181)
+ * start 0xF000000 (vr4122)
*/
#define BCUCNT1_REG_W 0x000 /* BCU Control Register 1 */
-#define BCUCNT1_ROMMASK (1<<15) /* ROM SIZE */
+#define BCUCNT1_ROMMASK (1<<15) /* ROM SIZE (<= 4121,>= 4102) */
#define BCUCNT1_ROM64M (1<<15) /* ROM SIZE 64Mbit*/
#define BCUCNT1_ROM32M (0<<15) /* ROM SIZE 32Mbit*/
-#define BCUCNT1_DRAMMASK (1<<14) /* DRAM SIZE */
+#define BCUCNT1_DRAMMASK (1<<14) /* DRAM SIZE (<= 4121,>= 4102) */
#define BCUCNT1_DRAM64M (1<<14) /* DRAM SIZE 64Mbit*/
#define BCUCNT1_DRAM32M (0<<14) /* DRAM SIZE 32Mbit*/
-#define BCUCNT1_ISAMLCD (1<<13) /* ISAM/LCD 0x0a000000 to 0xaffffff*/
+#define BCUCNT1_ISAMLCD (1<<13) /* ISAM/LCD 0x0a000000 to 0xaffffff(>= 4102) */
#define BCUCNT1_ISA (1<<13) /* ISA memory space */
#define BCUCNT1_LCD (0<<13) /* LCD space*/
-#define BCUCNT1_PAGEMASK (1<<12) /* Maximum burst access size for Page Rom */
+#define BCUCNT1_PAGEMASK (1<<12) /* Maximum burst access size for Page Rom (<= 4121,>= 4102) */
#define BCUCNT1_PAGE128 (1<<12) /* 128bit */
#define BCUCNT1_PAGE64 (0<<12) /* 64bit */
-#define BCUCNT1_PAGE2MASK (1<<10) /* */
+#define BCUCNT1_PAGESIZEMASK (3<<12) /* PageROM PAGESIZE (= 4122) */
+#define BCUCNT1_PASESIZE32 (2<<12) /* 32 byte */
+#define BCUCNT1_PASESIZE16 (1<<12) /* 16 byte */
+#define BCUCNT1_PASESIZE8 (0<<12) /* 8 byte */
+
+#define BCUCNT1_PAGE2MASK (1<<10) /* (<= 4122,>= 4102) */
#define BCUCNT1_PAGE2PAGE (1<<10) /* Page ROM */
#define BCUCNT1_PAGE2ORD (0<<10) /* Prginary ROM */
-#define BCUCNT1_PAGE0MASK (1<<8) /* */
+#define BCUCNT1_PAGE0MASK (1<<8) /* (<= 4122,>= 4102) */
#define BCUCNT1_PAGE0PAGE (1<<8) /* Page ROM */
#define BCUCNT1_PAGE0ORD (0<<8) /* Prginary ROM */
-#define BCUCNT1_ROMWEN2 (1<<6) /* Enable Flash memory write ROM 2*/
+#define BCUCNT1_REFMASK (1<<7) /* DRAM refresh interval (= 4101) */
+#define BCUCNT1_REF1024 (1<<7) /* 1024 cycles/128ms */
+#define BCUCNT1_REF4096 (0<<7) /* 4096 cycles/128ms */
+
+#define BCUCNT1_ROMWEN2 (1<<6) /* Enable Flash memory write ROM 2 (<= 4122,>= 4102) */
#define BCUCNT1_ROMWEN2EN (1<<6) /* Enable */
#define BCUCNT1_ROMWEN2DS (0<<6) /* Prohibit */
-#define BCUCNT1_ROMWEN0 (1<<4) /* Enable Flash memory write ROM 0*/
+#define BCUCNT1_PAGEROM (1<<6) /* Enable page ROM access (= 4101) */
+#define BCUCNT1_PAGEROMEN (1<<6) /* Page ROM */
+#define BCUCNT1_PAGEROMDIS (0<<6) /* not Page ROM */
+
+#define BCUCNT1_ROMWEN (1<<5) /* Enable Flash memory write ROM 0 (= 4101) */
+#define BCUCNT1_ROMWENEN (1<<5) /* Enable */
+#define BCUCNT1_ROMWENDS (0<<5) /* Prohibit */
+
+#define BCUCNT1_ROMWEN0 (1<<4) /* Enable Flash memory write ROM 0 (<= 4122,>= 4102) */
#define BCUCNT1_ROMWEN0EN (1<<4) /* Enable */
#define BCUCNT1_ROMWEN0DS (0<<4) /* Prohibit */
-#define BCUCNT1_BUSHERR (1<<1) /* Bus Timeout detection enable */
+#define BCUCNT1_SRFSTAT (1<<4) /* DRAM refresh mode (= 4101) */
+#define BCUCNT1_SRFSTATSRF (1<<4) /* self refresh */
+#define BCUCNT1_SRFSTATCBR (0<<4) /* CBR refresh */
+
+#define BCUCNT1_BCPUR (1<<3) /* CPU bus cycle control (= 4101) */
+#define BCUCNT1_BCPUREN (1<<3) /* CPU bus cycle control enable */
+#define BCUCNT1_BCPURDIS (0<<3) /* CPU bus cycle control disable */
+
+#define BCUCNT1_HLD (1<<2) /* Bus hold enable (= 4122) */
+#define BCUCNT1_HLDEN (1<<2) /* enable */
+#define BCUCNT1_HLDDIS (1<<2) /* disable */
+
+#define BCUCNT1_BUSHERR (1<<1) /* Bus Timeout detection enable (<= 4121,>= 4102) */
#define BCUCNT1_BUSHERREN (1<<1) /* Enable */
#define BCUCNT1_BUSHERRDS (0<<1) /* Prohibit */
@@ -83,12 +114,195 @@
#define BCUCNT1_RSTOUTL (0) /* RSTOUT low level*/
-#define BCUCNT2_REG_W 0x002 /* BCU Control Register 2 */
+#define BCUCNT2_REG_W 0x002 /* BCU Control Register 2 (<= 4121,>= 4102) */
#define BCUCNT2_GMODE (1) /* LCD access control */
#define BCUCNT2_GMODENOM (1) /* not invert LCD */
#define BCUCNT2_GMODEINV (0) /* invert LCD */
+#define BCUBR_REG_W 0x002 /* BCU Bus Restrain Register (= 4101) */
+
+#define BCUROMSIZE_REG_W 0x004 /* ROM size setting register (= 4122) */
+#define BCUROMSIZE_SIZE3 (7<<12) /* Bank3 size */
+#define BCUROMSIZE_SIZE3_64 (5<<12) /* 64MB */
+#define BCUROMSIZE_SIZE3_32 (4<<12) /* 32MB */
+#define BCUROMSIZE_SIZE3_16 (3<<12) /* 16MB */
+#define BCUROMSIZE_SIZE3_8 (2<<12) /* 8MB */
+#define BCUROMSIZE_SIZE3_4 (1<<12) /* 4MB */
+
+#define BCUROMSIZE_SIZE2 (7<<8) /* Bank2 size */
+#define BCUROMSIZE_SIZE2_64 (5<<8) /* 64MB */
+#define BCUROMSIZE_SIZE2_32 (4<<8) /* 32MB */
+#define BCUROMSIZE_SIZE2_16 (3<<8) /* 16MB */
+#define BCUROMSIZE_SIZE2_8 (2<<8) /* 8MB */
+#define BCUROMSIZE_SIZE2_4 (1<<8) /* 4MB */
+
+#define BCUROMSIZE_SIZE1 (7<<4) /* Bank1 size */
+#define BCUROMSIZE_SIZE1_64 (5<<4) /* 64MB */
+#define BCUROMSIZE_SIZE1_32 (4<<4) /* 32MB */
+#define BCUROMSIZE_SIZE1_16 (3<<4) /* 16MB */
+#define BCUROMSIZE_SIZE1_8 (2<<4) /* 8MB */
+#define BCUROMSIZE_SIZE1_4 (1<<4) /* 4MB */
+
+#define BCUROMSIZE_SIZE0 (7) /* Bank0 size */
+#define BCUROMSIZE_SIZE0_64 (5) /* 64MB */
+#define BCUROMSIZE_SIZE0_32 (4) /* 32MB */
+#define BCUROMSIZE_SIZE0_16 (3) /* 16MB */
+#define BCUROMSIZE_SIZE0_8 (2) /* 8MB */
+#define BCUROMSIZE_SIZE0_4 (1) /* 4MB */
+
+#define BCUBRCNT_REG_W 0x004 /* BCU Bus Restrain Count Register (= 4101) */
+
+#define BCUROMSPEED_REG_W 0x006 /* BCU ROM Speed Register (=4122) */
+#define BCUROMSPEED_PATIME (0x3<<12) /* Page Access time */
+#define BCUROMSPEED_PATIME_5VT (0x3<<12) /* 5VTClock */
+#define BCUROMSPEED_PATIME_4VT (0x2<<12) /* 4VTClock */
+#define BCUROMSPEED_PATIME_3VT (0x1<<12) /* 3VTClock */
+#define BCUROMSPEED_PATIME_2VT (0x0<<12) /* 2VTClock */
+
+#define BCUROMSPEED_ATIME (0xf) /* Access time */
+#define BCUROMSPEED_ATIME_18VT (0xf) /* 18VTClock */
+#define BCUROMSPEED_ATIME_17VT (0xe) /* 17VTClock */
+#define BCUROMSPEED_ATIME_16VT (0xd) /* 16VTClock */
+#define BCUROMSPEED_ATIME_15VT (0xc) /* 15VTClock */
+#define BCUROMSPEED_ATIME_14VT (0xb) /* 14VTClock */
+#define BCUROMSPEED_ATIME_13VT (0xa) /* 13VTClock */
+#define BCUROMSPEED_ATIME_12VT (0x9) /* 12VTClock */
+#define BCUROMSPEED_ATIME_11VT (0x8) /* 11VTClock */
+#define BCUROMSPEED_ATIME_10VT (0x7) /* 10VTClock */
+#define BCUROMSPEED_ATIME_9VT (0x6) /* 9VTClock */
+#define BCUROMSPEED_ATIME_8VT (0x5) /* 8VTClock */
+#define BCUROMSPEED_ATIME_7VT (0x4) /* 7VTClock */
+#define BCUROMSPEED_ATIME_6VT (0x3) /* 6VTClock */
+#define BCUROMSPEED_ATIME_5VT (0x2) /* 5VTClock */
+#define BCUROMSPEED_ATIME_4VT (0x1) /* 4VTClock */
+#define BCUROMSPEED_ATIME_3VT (0x0) /* 3VTClock */
+
+#define BCUBCL_REG_W 0x006 /* BCU CPU Restrain Disable Register (= 4101) */
+
+#define BCUIO0SPEED_REG_W 0x008 /* BCU IO0 Speed Register (=4122) */
+#define BCUIO0SPEED_RWCS (0x3<<12) /* R/W - CS time */
+#define BCUIO0SPEED_RWCS_5VT (0x3<<12) /* 5VTClock */
+#define BCUIO0SPEED_RWCS_4VT (0x2<<12) /* 4VTClock */
+#define BCUIO0SPEED_RWCS_3VT (0x1<<12) /* 3VTClock */
+#define BCUIO0SPEED_RWCS_2VT (0x0<<12) /* 2VTClock */
+
+#define BCUIO0SPEED_RDYRW (0xf<<8) /* IORDY-R/W time */
+#define BCUIO0SPEED_RDYRW_18VT (0xf) /* 18VTClock */
+#define BCUIO0SPEED_RDYRW_17VT (0xe) /* 17VTClock */
+#define BCUIO0SPEED_RDYRW_16VT (0xd) /* 16VTClock */
+#define BCUIO0SPEED_RDYRW_15VT (0xc) /* 15VTClock */
+#define BCUIO0SPEED_RDYRW_14VT (0xb) /* 14VTClock */
+#define BCUIO0SPEED_RDYRW_13VT (0xa) /* 13VTClock */
+#define BCUIO0SPEED_RDYRW_12VT (0x9) /* 12VTClock */
+#define BCUIO0SPEED_RDYRW_11VT (0x8) /* 11VTClock */
+#define BCUIO0SPEED_RDYRW_10VT (0x7) /* 10VTClock */
+#define BCUIO0SPEED_RDYRW_9VT (0x6) /* 9VTClock */
+#define BCUIO0SPEED_RDYRW_8VT (0x5) /* 8VTClock */
+#define BCUIO0SPEED_RDYRW_7VT (0x4) /* 7VTClock */
+#define BCUIO0SPEED_RDYRW_6VT (0x3) /* 6VTClock */
+#define BCUIO0SPEED_RDYRW_5VT (0x2) /* 5VTClock */
+#define BCUIO0SPEED_RDYRW_4VT (0x1) /* 4VTClock */
+#define BCUIO0SPEED_RDYRW_3VT (0x0) /* 3VTClock */
+
+#define BCUIO0SPEED_RWRDY (0xf<<4) /* R/W-IORDY time */
+#define BCUIO0SPEED_RWRDY_14VT (0xf) /* 14VTClock */
+#define BCUIO0SPEED_RWRDY_13VT (0xe) /* 13VTClock */
+#define BCUIO0SPEED_RWRDY_12VT (0xd) /* 12VTClock */
+#define BCUIO0SPEED_RWRDY_11VT (0xc) /* 11VTClock */
+#define BCUIO0SPEED_RWRDY_10VT (0xb) /* 10VTClock */
+#define BCUIO0SPEED_RWRDY_9VT (0xa) /* 9VTClock */
+#define BCUIO0SPEED_RWRDY_8VT (0x9) /* 8VTClock */
+#define BCUIO0SPEED_RWRDY_7VT (0x8) /* 7VTClock */
+#define BCUIO0SPEED_RWRDY_6VT (0x7) /* 6VTClock */
+#define BCUIO0SPEED_RWRDY_5VT (0x6) /* 5VTClock */
+#define BCUIO0SPEED_RWRDY_4VT (0x5) /* 4VTClock */
+#define BCUIO0SPEED_RWRDY_3VT (0x4) /* 3VTClock */
+#define BCUIO0SPEED_RWRDY_2VT (0x3) /* 2VTClock */
+#define BCUIO0SPEED_RWRDY_1VT (0x2) /* 1VTClock */
+#define BCUIO0SPEED_RWRDY_0VT (0x1) /* 0VTClock */
+#define BCUIO0SPEED_RWRDY_M1VT (0x0) /* -1VTClock */
+
+#define BCUIO0SPEED_CSRW (0xf<<0) /* IORDY-R/W time */
+#define BCUIO0SPEED_CSRW_16VT (0xf) /* 16VTClock */
+#define BCUIO0SPEED_CSRW_15VT (0xe) /* 15VTClock */
+#define BCUIO0SPEED_CSRW_14VT (0xd) /* 14VTClock */
+#define BCUIO0SPEED_CSRW_13VT (0xc) /* 13VTClock */
+#define BCUIO0SPEED_CSRW_12VT (0xb) /* 12VTClock */
+#define BCUIO0SPEED_CSRW_11VT (0xa) /* 11VTClock */
+#define BCUIO0SPEED_CSRW_10VT (0x9) /* 10VTClock */
+#define BCUIO0SPEED_CSRW_9VT (0x8) /* 9VTClock */
+#define BCUIO0SPEED_CSRW_8VT (0x7) /* 8VTClock */
+#define BCUIO0SPEED_CSRW_7VT (0x6) /* 7VTClock */
+#define BCUIO0SPEED_CSRW_6VT (0x5) /* 6VTClock */
+#define BCUIO0SPEED_CSRW_5VT (0x4) /* 5VTClock */
+#define BCUIO0SPEED_CSRW_4VT (0x3) /* 4VTClock */
+#define BCUIO0SPEED_CSRW_3VT (0x2) /* 3VTClock */
+#define BCUIO0SPEED_CSRW_2VT (0x1) /* 2VTClock */
+#define BCUIO0SPEED_CSRW_1VT (0x0) /* 1VTClock */
+
+#define BCUBCLCNT_REG_W 0x008 /* BCU CPU Restrain Disable Count Register (= 4101) */
+
+#define BCUIO1SPEED_REG_W 0x00A /* BCU IO1 Speed Register (=4122) */
+#define BCUIO1SPEED_RWCS (0x3<<12) /* R/W - CS time */
+#define BCUIO1SPEED_RWCS_5VT (0x3<<12) /* 5VTClock */
+#define BCUIO1SPEED_RWCS_4VT (0x2<<12) /* 4VTClock */
+#define BCUIO1SPEED_RWCS_3VT (0x1<<12) /* 3VTClock */
+#define BCUIO1SPEED_RWCS_2VT (0x0<<12) /* 2VTClock */
+
+#define BCUIO1SPEED_RDYRW (0xf<<8) /* IORDY-R/W time */
+#define BCUIO1SPEED_RDYRW_18VT (0xf) /* 18VTClock */
+#define BCUIO1SPEED_RDYRW_17VT (0xe) /* 17VTClock */
+#define BCUIO1SPEED_RDYRW_16VT (0xd) /* 16VTClock */
+#define BCUIO1SPEED_RDYRW_15VT (0xc) /* 15VTClock */
+#define BCUIO1SPEED_RDYRW_14VT (0xb) /* 14VTClock */
+#define BCUIO1SPEED_RDYRW_13VT (0xa) /* 13VTClock */
+#define BCUIO1SPEED_RDYRW_12VT (0x9) /* 12VTClock */
+#define BCUIO1SPEED_RDYRW_11VT (0x8) /* 11VTClock */
+#define BCUIO1SPEED_RDYRW_10VT (0x7) /* 10VTClock */
+#define BCUIO1SPEED_RDYRW_9VT (0x6) /* 9VTClock */
+#define BCUIO1SPEED_RDYRW_8VT (0x5) /* 8VTClock */
+#define BCUIO1SPEED_RDYRW_7VT (0x4) /* 7VTClock */
+#define BCUIO1SPEED_RDYRW_6VT (0x3) /* 6VTClock */
+#define BCUIO1SPEED_RDYRW_5VT (0x2) /* 5VTClock */
+#define BCUIO1SPEED_RDYRW_4VT (0x1) /* 4VTClock */
+#define BCUIO1SPEED_RDYRW_3VT (0x0) /* 3VTClock */
+
+#define BCUIO1SPEED_RWRDY (0xf<<4) /* R/W-IORDY time */
+#define BCUIO1SPEED_RWRDY_14VT (0xf) /* 14VTClock */
+#define BCUIO1SPEED_RWRDY_13VT (0xe) /* 13VTClock */
+#define BCUIO1SPEED_RWRDY_12VT (0xd) /* 12VTClock */
+#define BCUIO1SPEED_RWRDY_11VT (0xc) /* 11VTClock */
+#define BCUIO1SPEED_RWRDY_10VT (0xb) /* 10VTClock */
+#define BCUIO1SPEED_RWRDY_9VT (0xa) /* 9VTClock */
+#define BCUIO1SPEED_RWRDY_8VT (0x9) /* 8VTClock */
+#define BCUIO1SPEED_RWRDY_7VT (0x8) /* 7VTClock */
+#define BCUIO1SPEED_RWRDY_6VT (0x7) /* 6VTClock */
+#define BCUIO1SPEED_RWRDY_5VT (0x6) /* 5VTClock */
+#define BCUIO1SPEED_RWRDY_4VT (0x5) /* 4VTClock */
+#define BCUIO1SPEED_RWRDY_3VT (0x4) /* 3VTClock */
+#define BCUIO1SPEED_RWRDY_2VT (0x3) /* 2VTClock */
+#define BCUIO1SPEED_RWRDY_1VT (0x2) /* 1VTClock */
+#define BCUIO1SPEED_RWRDY_0VT (0x1) /* 0VTClock */
+#define BCUIO1SPEED_RWRDY_M1VT (0x0) /* -1VTClock */
+
+#define BCUIO1SPEED_CSRW (0xf<<0) /* IORDY-R/W time */
+#define BCUIO1SPEED_CSRW_16VT (0xf) /* 16VTClock */
+#define BCUIO1SPEED_CSRW_15VT (0xe) /* 15VTClock */
+#define BCUIO1SPEED_CSRW_14VT (0xd) /* 14VTClock */
+#define BCUIO1SPEED_CSRW_13VT (0xc) /* 13VTClock */
+#define BCUIO1SPEED_CSRW_12VT (0xb) /* 12VTClock */
+#define BCUIO1SPEED_CSRW_11VT (0xa) /* 11VTClock */
+#define BCUIO1SPEED_CSRW_10VT (0x9) /* 10VTClock */
+#define BCUIO1SPEED_CSRW_9VT (0x8) /* 9VTClock */
+#define BCUIO1SPEED_CSRW_8VT (0x7) /* 8VTClock */
+#define BCUIO1SPEED_CSRW_7VT (0x6) /* 7VTClock */
+#define BCUIO1SPEED_CSRW_6VT (0x5) /* 6VTClock */
+#define BCUIO1SPEED_CSRW_5VT (0x4) /* 5VTClock */
+#define BCUIO1SPEED_CSRW_4VT (0x3) /* 4VTClock */
+#define BCUIO1SPEED_CSRW_3VT (0x2) /* 3VTClock */
+#define BCUIO1SPEED_CSRW_2VT (0x1) /* 2VTClock */
+#define BCUIO1SPEED_CSRW_1VT (0x0) /* 1VTClock */
#define BCUSPEED_REG_W 0x00A /* BCU Access Cycle Change Register */
@@ -98,26 +312,26 @@
#define BCUSPD_WPROM2T (0x1<<12) /* 2TClock */
#define BCUSPD_WPROM3T (0x0<<12) /* 3TClock */
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