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[src/trunk]: src/sys/arch Rename the CLI/STI/ECLI/ESTI macros to more descrip...
details: https://anonhg.NetBSD.org/src/rev/b2cc1dfdb80d
branches: trunk
changeset: 503418:b2cc1dfdb80d
user: thorpej <thorpej%NetBSD.org@localhost>
date: Mon Feb 05 18:14:42 2001 +0000
description:
Rename the CLI/STI/ECLI/ESTI macros to more descriptive names,
and add comments to describe exactly what they do (because it's
not totally obvious at a glance, due to the number juggling necessary
to frob the correct bits in SR):
CLI -> EXCEPT_DISABLE (sets SR.BL)
STI -> EXCEPT_ENABLE (clears SR.BL)
ECLI -> INTR_DISABLE (sets SR.I[0-3])
ESTI -> INTR_ENABLE (clears SR.I[0-3])
diffstat:
sys/arch/dreamcast/dreamcast/locore.s | 90 ++++++++++++++++++----------------
sys/arch/evbsh3/evbsh3/locore.s | 88 +++++++++++++++++----------------
sys/arch/hpcsh/hpcsh/locore.s | 88 +++++++++++++++++----------------
sys/arch/mmeye/mmeye/locore.s | 88 +++++++++++++++++----------------
4 files changed, 185 insertions(+), 169 deletions(-)
diffs (truncated from 1257 to 300 lines):
diff -r 61e3fadcd25d -r b2cc1dfdb80d sys/arch/dreamcast/dreamcast/locore.s
--- a/sys/arch/dreamcast/dreamcast/locore.s Mon Feb 05 17:39:45 2001 +0000
+++ b/sys/arch/dreamcast/dreamcast/locore.s Mon Feb 05 18:14:42 2001 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.4 2001/01/30 01:32:56 msaitoh Exp $ */
+/* $NetBSD: locore.s,v 1.5 2001/02/05 18:14:42 thorpej Exp $ */
/*-
* Copyright (c) 1993, 1994, 1995, 1997
@@ -185,10 +185,10 @@
mov.l r0, @-r15
/*
- * emulate x86 cli, sti, ecli, esti
+ * Macros to disable and enable exceptions (inclding interrupts).
+ * This modifies SR.BL
*/
-
-#define CLI \
+#define EXCEPT_DISABLE \
mov.l r0, @-r15 ; \
mov.l r1, @-r15 ; \
mov #0x10, r0 ; \
@@ -196,11 +196,11 @@
swap.w r0, r0 ; /* r0 = 0x10000000 */ \
stc sr, r1 ; \
or r0, r1 ; \
- ldc r1, sr ; /* disable interrupt */ \
+ ldc r1, sr ; /* disable exceptions */ \
mov.l @r15+, r1 ; \
mov.l @r15+, r0
-#define STI \
+#define EXCEPT_ENABLE \
mov.l r0, @-r15 ; \
mov.l r1, @-r15 ; \
mov #0x10, r0 ; \
@@ -209,11 +209,15 @@
not r0, r0 ; \
stc sr, r1 ; \
and r0, r1 ; \
- ldc r1, sr ; /* enable interrupt */ \
+ ldc r1, sr ; /* enable exceptions */ \
mov.l @r15+, r1 ; \
mov.l @r15+, r0
-#define ECLI \
+/*
+ * Macros to disable and enable interrupts.
+ * This modifies SR.I[0-3]
+ */
+#define INTR_DISABLE \
mov.l r0, @-r15 ; \
mov.l r1, @-r15 ; \
mov #0x78, r0 ; \
@@ -224,7 +228,7 @@
mov.l @r15+, r1 ; \
mov.l @r15+, r0
-#define ESTI \
+#define INTR_ENABLE \
mov.l r0, @-r15 ; \
mov.l r1, @-r15 ; \
mov #0x78, r0 ; \
@@ -277,7 +281,7 @@
/* Set SP to initial position */
mov.l XLtmpstk, r15
- ECLI
+ INTR_DISABLE
/* Set Register Bank to Bank 0 */
mov.l SR_init, r0
@@ -432,7 +436,7 @@
jsr @r12
nop
add #4, r15 /* pop tf_trapno */
- CLI
+ EXCEPT_DISABLE
INTRFASTEXIT
/* NOTREACHED */
@@ -520,10 +524,10 @@
ENTRY(idle)
/*
- * When we get here, interrupts are off (via ECLI) and
+ * When we get here, interrupts are off (via INTR_DISABLE) and
* sched_lock is held.
*/
- STI
+ EXCEPT_ENABLE
mov.l XXLwhichqs, r0
mov.l @r0, r0
@@ -536,11 +540,11 @@
jsr @r0
nop
#endif
- ESTI
+ INTR_ENABLE
sleep
- ECLI
+ INTR_DISABLE
#if defined(LOCKDEBUG)
mov.l Xsched_lock, r0
jsr @r0
@@ -731,7 +735,7 @@
*/
/* Lock the scheduler. */
- ECLI /* splhigh doesn't do a cli */
+ INTR_DISABLE /* splhigh doesn't do a cli */
#if defined(LOCKDEBUG)
mov.l Xsched_lock, r0
jsr @r0
@@ -949,7 +953,7 @@
mov.l r8, @r0
/* It's okay to take interrupts here. */
- ESTI
+ INTR_ENABLE
/* Skip context switch if same process. */
mov r12, r0 /* r12 = oldCurproc */
@@ -990,7 +994,7 @@
*/
/* No interrupts while loading new state. */
- ECLI
+ INTR_DISABLE
mov r8, r4 /* r8 = qs[i]->p_forw */
mov.l XLP_ADDR, r1
add r1, r4
@@ -1045,7 +1049,7 @@
mov.l r12, @r0
/* Interrupts are okay again. */
- ESTI
+ INTR_ENABLE
switch_return:
/*
@@ -1098,7 +1102,7 @@
mov.l r0, @r1
/* Restore proc0's context. */
- ECLI
+ INTR_DISABLE
mov r9, r0
mov.l XXLP_ADDR, r1
add r1, r0
@@ -1133,7 +1137,7 @@
mov.l r10, @r0
/* Interrupts are okay again. */
- ESTI
+ INTR_ENABLE
mov r8, r4
mov.l XLexit2, r0
@@ -1238,8 +1242,8 @@
mov.l XL_SHREG_EXPEVT, r0
mov.l @r0, r0
mov.l r0, @-r15
- ESTI
- STI
+ INTR_ENABLE
+ EXCEPT_ENABLE
mov.l XL_trap, r0
jsr @r0
nop
@@ -1247,7 +1251,7 @@
nop
2: /* Check for ASTs on exit to user mode. */
- ECLI
+ INTR_DISABLE
mov.l XL_astpending, r0
mov.l @r0, r0
tst r0, r0
@@ -1266,7 +1270,7 @@
mov.l XL_astpending, r1
mov.l r0, @r1
- ESTI
+ INTR_ENABLE
mov.l XLT_ASTFLT, r1
mov.l r1, @-r15
@@ -1277,7 +1281,7 @@
bra 2b
nop
1:
- CLI
+ EXCEPT_DISABLE
#ifdef DDB
mov.l @r15, r0
@@ -1323,15 +1327,15 @@
XL_splimit_low3: .long 0x80000000
100:
#endif
- ECLI
- /* we must permit interrupt to enable address translation */
- STI
+ INTR_DISABLE
+ /* we must permit exceptions to enable address translation */
+ EXCEPT_ENABLE
mov.l r0, @-r15 /* push dummy trap code */
mov.l XL_tlb_handler, r0
jsr @r0
nop
add #4, r15 /* pop dummy code */
- CLI
+ EXCEPT_DISABLE
ldtlb
INTRFASTEXIT
@@ -1525,8 +1529,8 @@
mov.l @r0, r0
mov.l r0, @-r15
6:
- ECLI /* disable external interrupt */
- STI /* enable exception for TLB handling */
+ INTR_DISABLE /* disable external interrupt */
+ EXCEPT_ENABLE /* enable exception for TLB handling */
mov.l XL_intrhandler, r0
jsr @r0
nop
@@ -1544,7 +1548,7 @@
bf 7b
2: /* Check for ASTs on exit to user mode. */
- ECLI
+ INTR_DISABLE
mov.l XXL_astpending, r0
mov.l @r0, r0
tst r0, r0
@@ -1562,7 +1566,7 @@
5: xor r0, r0
mov.l XXL_astpending, r1
mov.l r0, @r1
- ESTI
+ INTR_ENABLE
mov.l XXLT_ASTFLT, r1
mov.l r1, @-r15
mov.l XXL_trap, r0
@@ -1572,7 +1576,7 @@
bra 2b
nop
1:
- CLI
+ EXCEPT_DISABLE
INTRFASTEXIT
.align 2
@@ -1584,22 +1588,22 @@
XL_check_ipending: .long _C_LABEL(check_ipending)
ENTRY(enable_interrupt)
- ESTI
+ INTR_ENABLE
rts
nop
ENTRY(disable_interrupt)
- ECLI
+ INTR_DISABLE
rts
nop
ENTRY(enable_ext_intr)
- ESTI
+ INTR_ENABLE
rts
nop
ENTRY(disable_ext_intr)
- ECLI
+ INTR_DISABLE
rts
nop
@@ -1608,8 +1612,8 @@
mov.l r1, @-r15
Xrestart:
- ECLI
- STI
+ INTR_DISABLE
+ EXCEPT_ENABLE
mov.l XXL_check_ipending, r0
jsr @r0
nop
@@ -1623,7 +1627,7 @@
nop
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