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[src/netbsd-1-6]: src/sys/arch/powerpc/mpc6xx Pull up revision 1.51 (requeste...
details: https://anonhg.NetBSD.org/src/rev/e1f6054b4ec2
branches: netbsd-1-6
changeset: 529319:e1f6054b4ec2
user: he <he%NetBSD.org@localhost>
date: Sun Nov 10 15:50:38 2002 +0000
description:
Pull up revision 1.51 (requested by matt in ticket #559):
Set normal memory PTEs with PTE_M (memory coherent). Change
how we remember the ``execness'' of a page, so that we can
avoid I-cache syncing in some cases.
diffstat:
sys/arch/powerpc/mpc6xx/pmap.c | 52 ++++++++++++++++++++++++++---------------
1 files changed, 33 insertions(+), 19 deletions(-)
diffs (108 lines):
diff -r c10cfbfd9839 -r e1f6054b4ec2 sys/arch/powerpc/mpc6xx/pmap.c
--- a/sys/arch/powerpc/mpc6xx/pmap.c Sun Nov 10 15:50:07 2002 +0000
+++ b/sys/arch/powerpc/mpc6xx/pmap.c Sun Nov 10 15:50:38 2002 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.c,v 1.43.4.2 2002/11/01 18:11:55 tron Exp $ */
+/* $NetBSD: pmap.c,v 1.43.4.3 2002/11/10 15:50:38 he Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -1394,11 +1394,11 @@
failed = 1;
}
if (((pvo->pvo_pte.pte_lo ^ pt->pte_lo) &
- (PTE_PP|PTE_W|PTE_I|PTE_G|PTE_RPGN)) != 0) {
+ (PTE_PP|PTE_WIMG|PTE_RPGN)) != 0) {
printf("pmap_pvo_check: pvo %p: pte_lo differ: %#x/%#x\n",
pvo,
- pvo->pvo_pte.pte_lo & (PTE_PP|PTE_W|PTE_I|PTE_G|PTE_RPGN),
- pt->pte_lo & (PTE_PP|PTE_W|PTE_I|PTE_G|PTE_RPGN));
+ pvo->pvo_pte.pte_lo & (PTE_PP|PTE_WIMG|PTE_RPGN),
+ pt->pte_lo & (PTE_PP|PTE_WIMG|PTE_RPGN));
failed = 1;
}
if (pmap_pte_to_va(pt) != PVO_VADDR(pvo)) {
@@ -1636,26 +1636,21 @@
* If this is a managed page, and it's the first reference to the
* page clear the execness of the page. Otherwise fetch the execness.
*/
- if (pg != NULL) {
- if (LIST_EMPTY(pvo_head)) {
- pmap_attr_clear(pg, PTE_EXEC);
- DPRINTFN(ENTER, (" first"));
- } else {
- was_exec = pmap_attr_fetch(pg) & PTE_EXEC;
- }
- }
+ if (pg != NULL)
+ was_exec = pmap_attr_fetch(pg) & PTE_EXEC;
DPRINTFN(ENTER, (" was_exec=%d", was_exec));
/*
* Assume the page is cache inhibited and access is guarded unless
- * it's in our available memory array.
+ * it's in our available memory array. If it is in the memory array,
+ * asssume it's in memory coherent memory.
*/
- pte_lo = PTE_I | PTE_G;
+ pte_lo = PTE_IG;
if ((flags & PMAP_NC) == 0) {
for (mp = mem; mp->size; mp++) {
if (pa >= mp->start && pa < mp->start + mp->size) {
- pte_lo &= ~(PTE_I | PTE_G);
+ pte_lo = PTE_M;
break;
}
}
@@ -1726,10 +1721,15 @@
DPRINTFN(KENTER,
("pmap_kenter_pa(%#lx,%#lx,%#x)\n", va, pa, prot));
- pte_lo = PTE_I | PTE_G;
+ /*
+ * Assume the page is cache inhibited and access is guarded unless
+ * it's in our available memory array. If it is in the memory array,
+ * asssume it's in memory coherent memory.
+ */
+ pte_lo = PTE_IG;
for (mp = mem; mp->size; mp++) {
if (pa >= mp->start && pa < mp->start + mp->size) {
- pte_lo &= ~(PTE_I | PTE_G);
+ pte_lo = PTE_M;
break;
}
}
@@ -1751,9 +1751,15 @@
/*
* Flush the real memory from the instruction cache.
+ * If it's writeable, clear the PTE_EXEC attribute.
*/
- if ((prot & VM_PROT_EXECUTE) && (pte_lo & (PTE_I|PTE_G)) == 0) {
- pmap_syncicache(pa, NBPG);
+ if (prot & VM_PROT_EXECUTE) {
+ if ((pte_lo & (PTE_IG)) == 0)
+ pmap_syncicache(pa, NBPG);
+ } else if (prot & VM_PROT_WRITE) {
+ struct vm_page *pg = PHYS_TO_VM_PAGE(pa);
+ if (pg != NULL)
+ pmap_attr_clear(pg, PTE_EXEC);
}
}
@@ -1943,6 +1949,14 @@
s = splvm();
msr = pmap_interrupts_off();
+ /*
+ * When UVM reuses a page, it does a pmap_page_protect with
+ * VM_PROT_NONE. At that point, we can clear the exec flag
+ * since we know the page will have different contents.
+ */
+ if ((prot & VM_PROT_READ) == 0)
+ pmap_attr_clear(pg, PTE_EXEC);
+
pvo_head = vm_page_to_pvoh(pg);
for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
next_pvo = LIST_NEXT(pvo, pvo_vlink);
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