[src/trunk]: src/sys/arch/sgimips/sgimips Hack: disable R5K L2 cache for now, ...

[soren <soren%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/dca868da690f
branches:  trunk
changeset: 494038:dca868da690f
user:      soren <soren%NetBSD.org@localhost>
date:      Thu Jun 29 15:18:41 2000 +0000

description:
Hack: disable R5K L2 cache for now, pending (working) changed cache ops.

diffstat:

 sys/arch/sgimips/sgimips/cpu.c |  16 ++++++++++++++--
 1 files changed, 14 insertions(+), 2 deletions(-)

diffs (45 lines):

diff -r b0b283e44b85 -r dca868da690f sys/arch/sgimips/sgimips/cpu.c
--- a/sys/arch/sgimips/sgimips/cpu.c    Thu Jun 29 15:16:17 2000 +0000
+++ b/sys/arch/sgimips/sgimips/cpu.c    Thu Jun 29 15:18:41 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpu.c,v 1.1 2000/06/14 16:02:44 soren Exp $    */
+/*     $NetBSD: cpu.c,v 1.2 2000/06/29 15:18:41 soren Exp $    */
 
 /*
  * Copyright (c) 2000 Soren S. Jorvang
@@ -63,17 +63,24 @@
        void *aux;
 {
        struct mainbus_attach_args *ma = aux;
+       u_int32_t config;
 
        if (ma->ma_arch == 32)
                mips_L2CacheSize = 512 * 1024;          /* XXX O2 */
 
+#if 1
+       config = mips3_read_config();
+       config &= ~MIPS3_CONFIG_SC;
+       mips3_write_config(config);
+#endif
+
        printf(": ");
        cpu_identify();
 
        if (ma->ma_arch == 22) {                        /* XXX Indy */
                unsigned long tmp1, tmp2, tmp3;
 
-               printf("cpu0: disabling auxiliary L2 cache\n");
+               printf("cpu0: disabling IP22 SysAD L2 cache\n");
 
                __asm__ __volatile__("
                 .set noreorder
@@ -97,4 +104,9 @@
                 .set reorder
                " : "=r" (tmp1), "=r" (tmp2), "=r" (tmp3));
        }
+
+#if 1
+       mips_L2CacheSize = 0;
+       mips_L2CachePresent = 0;
+#endif
 }