[src/trunk]: src/sys/arch/arm/xscale As per the recent ixp425 fix (which is b...

[scw <scw%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/97fd2a377b65
branches:  trunk
changeset: 555888:97fd2a377b65
user:      scw <scw%NetBSD.org@localhost>
date:      Wed Dec 03 19:55:37 2003 +0000

description:
As per the recent ixp425 fix (which is based on this code):

In the interrupt dispatch loop, make sure to handle any pending interrupts
which came in while we were dealing with the first interrupt(s), and which
are enabled at the current spl.

This fixes a problem where the intr_enabled/hw mask is not updated to
allow pending interrupts through until the next splx(). In some case,
interrupts could be delayed until the next clock tick.

diffstat:

 sys/arch/arm/xscale/i80321_icu.c |  10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)

diffs (31 lines):

diff -r 05c2e95b0563 -r 97fd2a377b65 sys/arch/arm/xscale/i80321_icu.c
--- a/sys/arch/arm/xscale/i80321_icu.c  Wed Dec 03 19:44:42 2003 +0000
+++ b/sys/arch/arm/xscale/i80321_icu.c  Wed Dec 03 19:55:37 2003 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: i80321_icu.c,v 1.8 2003/07/15 00:24:53 lukem Exp $     */
+/*     $NetBSD: i80321_icu.c,v 1.9 2003/12/03 19:55:37 scw Exp $       */
 
 /*
  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: i80321_icu.c,v 1.8 2003/07/15 00:24:53 lukem Exp $");
+__KERNEL_RCSID(0, "$NetBSD: i80321_icu.c,v 1.9 2003/12/03 19:55:37 scw Exp $");
 
 #ifndef EVBARM_SPL_NOINLINE
 #define        EVBARM_SPL_NOINLINE
@@ -513,6 +513,12 @@
                /* Re-enable this interrupt now that's it's cleared. */
                intr_enabled |= ibit;
                i80321_set_intrmask();
+
+               /*
+                * Don't forget to include interrupts which may have
+                * arrived in the meantime.
+                */
+               hwpend |= ((i80321_ipending & ICU_INT_HWMASK) & ~pcpl);
        }
 
        /* Check for pendings soft intrs. */