[src/netbsd-2-0]: src/sys/dev/pci Pull up revision 1.12 (requested by thorpej...

[jdc <jdc%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/50cb3ff0a9b6
branches:  netbsd-2-0
changeset: 564640:50cb3ff0a9b6
user:      jdc <jdc%NetBSD.org@localhost>
date:      Fri Jan 07 11:43:29 2005 +0000

description:
Pull up revision 1.12 (requested by thorpej in ticket #897)

- Add some useful constants related to the Packet Buffer Allocation
  register.
- Add the Receive and Transmit Data FIFO registers.

diffstat:

 sys/dev/pci/if_wmreg.h |  28 +++++++++++++++++++++++++++-
 1 files changed, 27 insertions(+), 1 deletions(-)

diffs (49 lines):

diff -r c342e78c4528 -r 50cb3ff0a9b6 sys/dev/pci/if_wmreg.h
--- a/sys/dev/pci/if_wmreg.h    Fri Jan 07 11:42:45 2005 +0000
+++ b/sys/dev/pci/if_wmreg.h    Fri Jan 07 11:43:29 2005 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_wmreg.h,v 1.10 2004/02/19 05:19:52 thorpej Exp $    */
+/*     $NetBSD: if_wmreg.h,v 1.10.2.1 2005/01/07 11:43:29 jdc Exp $    */
 
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
@@ -491,6 +491,24 @@
 #define        WMREG_TQC       0x0418
 
 #define        WMREG_OLD_TBDAL 0x0420  /* Transmit Descriptor Base Lo */
+#define        WMREG_RDFH      0x2410  /* Receive Data FIFO Head */
+
+#define        WMREG_RDFT      0x2418  /* Receive Data FIFO Tail */
+
+#define        WMREG_RDFHS     0x2420  /* Receive Data FIFO Head Saved */
+
+#define        WMREG_RDFTS     0x2428  /* Receive Data FIFO Tail Saved */
+
+#define        WMREG_TDFH      0x3410  /* Transmit Data FIFO Head */
+
+#define        WMREG_TDFT      0x3418  /* Transmit Data FIFO Tail */
+
+#define        WMREG_TDFHS     0x3420  /* Transmit Data FIFO Head Saved */
+
+#define        WMREG_TDFTS     0x3428  /* Transmit Data FIFO Tail Saved */
+
+#define        WMREG_TDFPC     0x3430  /* Transmit Data FIFO Packet Count */
+
 #define        WMREG_TBDAL     0x3800
 
 #define        WMREG_OLD_TBDAH 0x0424  /* Transmit Descriptor Base Hi */
@@ -522,6 +540,14 @@
 
 #define        WMREG_PBA       0x1000  /* Packet Buffer Allocation */
 
+#define        PBA_BYTE_SHIFT  10              /* KB -> bytes */
+#define        PBA_ADDR_SHIFT  7               /* KB -> quadwords */
+#define        PBA_16K         0x0010          /* 16K, default Tx allocation */
+#define        PBA_22K         0x0016
+#define        PBA_24K         0x0018
+#define        PBA_30K         0x001e
+#define        PBA_40K         0x0028
+#define        PBA_48K         0x0030          /* 48K, default Rx allocation */
 #define        WMREG_TXDMAC    0x3000  /* Transfer DMA Control */
 #define        TXDMAC_DPP      (1U << 0)       /* disable packet prefetch */