[src/trunk]: src/sys/arch/arm/arm32 Back out previous. There were several pr...

[thorpej <thorpej%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/30d4d46dfde7
branches:  trunk
changeset: 546092:30d4d46dfde7
user:      thorpej <thorpej%NetBSD.org@localhost>
date:      Sun Apr 20 15:42:51 2003 +0000

description:
Back out previous.  There were several problems with the patch that
was checked in:
* It was not actually disabling the MMU, and so jumping to the
  reset vector would happily cause a panic(), since it would be
  the kernel's reset vector, not the ROM's.
* In the event the system was using high vectors, VECRELOC was not
  getting cleared, which has the potential to wreak havoc when re-entering
  the ROM.
* It was totally broken for CPUs < ARMv4; you still need to disable
  the MMU on those, just need to skip the ARMv4 TLB flush.
* The code that was checked in would only work if the kernel is mapped
  VA==PA.  For systems where the kernel is NOT mapped VA==PA, you only
  get the prefetch depth # of insns (2) after the MMU is turned off before
  you have fix the PC.

Backing out the change fixes rebooting on several evbarm platforms.

diffstat:

 sys/arch/arm/arm32/locore.S |  10 +++-------
 1 files changed, 3 insertions(+), 7 deletions(-)

diffs (30 lines):

diff -r 7bae69e617cb -r 30d4d46dfde7 sys/arch/arm/arm32/locore.S
--- a/sys/arch/arm/arm32/locore.S       Sun Apr 20 15:32:10 2003 +0000
+++ b/sys/arch/arm/arm32/locore.S       Sun Apr 20 15:42:51 2003 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.12 2003/03/26 17:36:56 mycroft Exp $      */
+/*     $NetBSD: locore.S,v 1.13 2003/04/20 15:42:51 thorpej Exp $      */
 
 /*
  * Copyright (C) 1994-1997 Mark Brinicombe
@@ -125,18 +125,14 @@
        ldr     r1, .Lcpu_reset_needs_v4_MMU_disable
        ldr     r1, [r1]
        cmp     r1, #0
-       moveq   pc, r4
 
        /*
         * MMU & IDC off, 32 bit program & data space
         * Hurl ourselves into the ROM
         */
-       mrc     15, 0, r0, c1, c0, 0
-       bic     r0, r0, #(CPU_CONTROL_DC_ENABLE|CPU_CONTROL_WBUF_ENABLE)
-       bic     r0, r0, #(CPU_CONTROL_SYST_ENABLE|CPU_CONTROL_IC_ENABLE)
+       mov     r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE)
        mcr     15, 0, r0, c1, c0, 0
-       mov     r0, #0
-       mcr     15, 0, r0, c8, c7, 0    /* nail I+D TLB on ARMv4 and greater */
+       mcrne   15, 0, r0, c8, c7, 0    /* nail I+D TLB on ARMv4 and greater */
        mov     pc, r4
 
        /*