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[src/netbsd-1-6]: src/sys/arch/arm/arm Pullup revs 1.2-1.6 (requested by chri...
details: https://anonhg.NetBSD.org/src/rev/b8856c5fefd5
branches: netbsd-1-6
changeset: 530112:b8856c5fefd5
user: jmc <jmc%NetBSD.org@localhost>
date: Mon Feb 10 06:09:50 2003 +0000
description:
Pullup revs 1.2-1.6 (requested by chris in ticket #1157)
Provide better stability for arm ports by reducing instances of
unaligned copying.
diffstat:
sys/arch/arm/arm/bcopyinout.S | 317 ++++++++++++++++++++---------------------
1 files changed, 158 insertions(+), 159 deletions(-)
diffs (truncated from 651 to 300 lines):
diff -r b26f7c684904 -r b8856c5fefd5 sys/arch/arm/arm/bcopyinout.S
--- a/sys/arch/arm/arm/bcopyinout.S Mon Feb 10 06:06:21 2003 +0000
+++ b/sys/arch/arm/arm/bcopyinout.S Mon Feb 10 06:09:50 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bcopyinout.S,v 1.9.4.2 2002/11/18 02:36:47 he Exp $ */
+/* $NetBSD: bcopyinout.S,v 1.9.4.3 2003/02/10 06:09:50 jmc Exp $ */
/*
* Copyright (c) 2002 Wasabi Systems, Inc.
@@ -38,12 +38,13 @@
#include "assym.h"
#include <machine/asm.h>
-#include <sys/errno.h>
+
+RCSID("$NetBSD: bcopyinout.S,v 1.9.4.3 2003/02/10 06:09:50 jmc Exp $")
.text
.align 0
-Lcurpcb:
+.Lcurpcb:
.word _C_LABEL(curpcb)
#ifdef __PROG32
@@ -79,11 +80,11 @@
moveq pc, lr
SAVE_REGS
- ldr r4, Lcurpcb
+ ldr r4, .Lcurpcb
ldr r4, [r4]
ldr r5, [r4, #PCB_ONFAULT]
- add r3, pc, #Lcopyfault - . - 8
+ add r3, pc, #.Lcopyfault - . - 8
str r3, [r4, #PCB_ONFAULT]
PREFETCH(r0, 0)
@@ -93,43 +94,43 @@
* If not too many bytes, take the slow path.
*/
cmp r2, #0x08
- blt Licleanup
+ blt .Licleanup
/*
* Align destination to word boundary.
*/
and r6, r1, #0x3
ldr pc, [pc, r6, lsl #2]
- b Lialend
- .word Lialend
- .word Lial1
- .word Lial2
- .word Lial3
-Lial3: ldrbt r6, [r0], #1
+ b .Lialend
+ .word .Lialend
+ .word .Lial3
+ .word .Lial2
+ .word .Lial1
+.Lial3: ldrbt r6, [r0], #1
sub r2, r2, #1
strb r6, [r1], #1
-Lial2: ldrbt r7, [r0], #1
+.Lial2: ldrbt r7, [r0], #1
sub r2, r2, #1
strb r7, [r1], #1
-Lial1: ldrbt r6, [r0], #1
+.Lial1: ldrbt r6, [r0], #1
sub r2, r2, #1
strb r6, [r1], #1
-Lialend:
+.Lialend:
/*
* If few bytes left, finish slow.
*/
cmp r2, #0x08
- blt Licleanup
+ blt .Licleanup
/*
* If source is not aligned, finish slow.
*/
ands r3, r0, #0x03
- bne Licleanup
+ bne .Licleanup
cmp r2, #0x60 /* Must be > 0x5f for unrolled cacheline */
- blt Licleanup8
+ blt .Licleanup8
/*
* Align destination to cacheline boundary.
@@ -139,34 +140,34 @@
*/
and r6, r1, #0x1f
ldr pc, [pc, r6]
- b Licaligned
- .word Licaligned
- .word Lical4
- .word Lical8
- .word Lical12
- .word Lical16
- .word Lical20
- .word Lical24
- .word Lical28
-Lical28:ldrt r6, [r0], #4
+ b .Licaligned
+ .word .Licaligned
+ .word .Lical28
+ .word .Lical24
+ .word .Lical20
+ .word .Lical16
+ .word .Lical12
+ .word .Lical8
+ .word .Lical4
+.Lical28:ldrt r6, [r0], #4
sub r2, r2, #4
str r6, [r1], #4
-Lical24:ldrt r7, [r0], #4
+.Lical24:ldrt r7, [r0], #4
sub r2, r2, #4
str r7, [r1], #4
-Lical20:ldrt r6, [r0], #4
+.Lical20:ldrt r6, [r0], #4
sub r2, r2, #4
str r6, [r1], #4
-Lical16:ldrt r7, [r0], #4
+.Lical16:ldrt r7, [r0], #4
sub r2, r2, #4
str r7, [r1], #4
-Lical12:ldrt r6, [r0], #4
+.Lical12:ldrt r6, [r0], #4
sub r2, r2, #4
str r6, [r1], #4
-Lical8: ldrt r7, [r0], #4
+.Lical8:ldrt r7, [r0], #4
sub r2, r2, #4
str r7, [r1], #4
-Lical4: ldrt r6, [r0], #4
+.Lical4:ldrt r6, [r0], #4
sub r2, r2, #4
str r6, [r1], #4
@@ -184,7 +185,7 @@
* bytes -= 0x20;
* copy cacheline
*/
-Licaligned:
+.Licaligned:
PREFETCH(r0, 32)
PREFETCH(r1, 32)
@@ -203,7 +204,7 @@
stmia r1!, {r6-r11}
cmp r2, #0x40
- bge Licaligned
+ bge .Licaligned
sub r2, r2, #0x20
@@ -220,47 +221,47 @@
stmia r1!, {r6-r11}
cmp r2, #0x08
- blt Liprecleanup
+ blt .Liprecleanup
-Licleanup8:
+.Licleanup8:
ldrt r8, [r0], #4
ldrt r9, [r0], #4
sub r2, r2, #8
stmia r1!, {r8, r9}
cmp r2, #8
- bge Licleanup8
+ bge .Licleanup8
-Liprecleanup:
+.Liprecleanup:
/*
* If we're done, bail.
*/
cmp r2, #0
- beq Lout
+ beq .Lout
-Licleanup:
+.Licleanup:
and r6, r2, #0x3
ldr pc, [pc, r6, lsl #2]
- b Licend
- .word Lic4
- .word Lic1
- .word Lic2
- .word Lic3
-Lic4: ldrbt r6, [r0], #1
+ b .Licend
+ .word .Lic4
+ .word .Lic1
+ .word .Lic2
+ .word .Lic3
+.Lic4: ldrbt r6, [r0], #1
sub r2, r2, #1
strb r6, [r1], #1
-Lic3: ldrbt r7, [r0], #1
+.Lic3: ldrbt r7, [r0], #1
sub r2, r2, #1
strb r7, [r1], #1
-Lic2: ldrbt r6, [r0], #1
+.Lic2: ldrbt r6, [r0], #1
sub r2, r2, #1
strb r6, [r1], #1
-Lic1: ldrbt r7, [r0], #1
+.Lic1: ldrbt r7, [r0], #1
subs r2, r2, #1
strb r7, [r1], #1
-Licend:
- bne Licleanup
+.Licend:
+ bne .Licleanup
-Liout:
+.Liout:
mov r0, #0
str r5, [r4, #PCB_ONFAULT]
@@ -268,9 +269,7 @@
mov pc, lr
-Lcopyfault:
- mov r0, #EFAULT
-
+.Lcopyfault:
str r5, [r4, #PCB_ONFAULT]
RESTORE_REGS
@@ -294,11 +293,11 @@
moveq pc, lr
SAVE_REGS
- ldr r4, Lcurpcb
+ ldr r4, .Lcurpcb
ldr r4, [r4]
ldr r5, [r4, #PCB_ONFAULT]
- add r3, pc, #Lcopyfault - . - 8
+ add r3, pc, #.Lcopyfault - . - 8
str r3, [r4, #PCB_ONFAULT]
PREFETCH(r0, 0)
@@ -308,77 +307,77 @@
* If not too many bytes, take the slow path.
*/
cmp r2, #0x08
- blt Lcleanup
+ blt .Lcleanup
/*
* Align destination to word boundary.
*/
and r6, r1, #0x3
ldr pc, [pc, r6, lsl #2]
- b Lalend
- .word Lalend
- .word Lal1
- .word Lal2
- .word Lal3
-Lal3: ldrb r6, [r0], #1
+ b .Lalend
+ .word .Lalend
+ .word .Lal3
+ .word .Lal2
+ .word .Lal1
+.Lal3: ldrb r6, [r0], #1
sub r2, r2, #1
strbt r6, [r1], #1
-Lal2: ldrb r7, [r0], #1
+.Lal2: ldrb r7, [r0], #1
sub r2, r2, #1
strbt r7, [r1], #1
-Lal1: ldrb r6, [r0], #1
+.Lal1: ldrb r6, [r0], #1
sub r2, r2, #1
strbt r6, [r1], #1
-Lalend:
+.Lalend:
/*
* If few bytes left, finish slow.
*/
cmp r2, #0x08
- blt Lcleanup
+ blt .Lcleanup
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