[src/trunk]: src/sys/dev/dec set odd parity for the serial line

[drochner <drochner%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/527bb3e3b33d
branches:  trunk
changeset: 476528:527bb3e3b33d
user:      drochner <drochner%NetBSD.org@localhost>
date:      Sun Sep 19 14:45:47 1999 +0000

description:
set odd parity for the serial line
(done by directly setting zilog chip control bits -- there should be
a zs_set_frame() or so in z8530sc.c)
fixes PR port-alpha/8423 by Konrad Schroder <perseant%hhhh.org@localhost>

diffstat:

 sys/dev/dec/zsms.c |  9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)

diffs (26 lines):

diff -r de2493f71f57 -r 527bb3e3b33d sys/dev/dec/zsms.c
--- a/sys/dev/dec/zsms.c        Sun Sep 19 13:00:13 1999 +0000
+++ b/sys/dev/dec/zsms.c        Sun Sep 19 14:45:47 1999 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: zsms.c,v 1.3 1999/02/03 20:22:28 mycroft Exp $ */
+/*     $NetBSD: zsms.c,v 1.4 1999/09/19 14:45:47 drochner Exp $        */
 
 /*
  * Copyright (c) 1992, 1993
@@ -165,10 +165,15 @@
        s = splzs();
        /* May need reset... */
        zs_write_reg(cs, 9, ZSWR9_A_RESET);
-       /* These are OK as set by zscc: WR3, WR4, WR5 */
+       /* These are OK as set by zscc: WR3, WR5 */
        /* We don't care about status or tx interrupts. */
        cs->cs_preg[1] = ZSWR1_RIE;
        (void) zs_set_speed(cs, ZSMS_BPS);
+
+       /* mouse wants odd parity */
+       cs->cs_preg[4] |= ZSWR4_PARENB;
+       /* cs->cs_preg[4] &= ~ZSWR4_EVENP; (no-op) */
+
        zs_loadchannelregs(cs);
        splx(s);