[src/trunk]: src/sys/arch/mips/mips Make sure we use index ops (instead of hi...

[simonb <simonb%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/56de20ffd116
branches:  trunk
changeset: 539179:56de20ffd116
user:      simonb <simonb%NetBSD.org@localhost>
date:      Sun Nov 10 11:11:39 2002 +0000

description:
Make sure we use index ops (instead of hit ops) in the range index
functions.
Fix typos in the cache_r4k_op_32_4way_load_off macro.

Both problems reported by Chris Demetriou.

diffstat:

 sys/arch/mips/mips/cache_mipsNN.c |  46 +++++++++++++++++++-------------------
 1 files changed, 23 insertions(+), 23 deletions(-)

diffs (123 lines):

diff -r 2ceb93295a85 -r 56de20ffd116 sys/arch/mips/mips/cache_mipsNN.c
--- a/sys/arch/mips/mips/cache_mipsNN.c Sun Nov 10 11:06:11 2002 +0000
+++ b/sys/arch/mips/mips/cache_mipsNN.c Sun Nov 10 11:11:39 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache_mipsNN.c,v 1.3 2002/11/08 07:35:20 cgd Exp $     */
+/*     $NetBSD: cache_mipsNN.c,v 1.4 2002/11/10 11:11:39 simonb Exp $  */
 
 /*
  * Copyright 2001 Wasabi Systems, Inc.
@@ -431,8 +431,8 @@
        }
 
        while (va < eva) {
-               cache_op_r4k_line(va,   CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
-               cache_op_r4k_line(w2va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
+               cache_op_r4k_line(va,   CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+               cache_op_r4k_line(w2va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
                va   += 16;
                w2va += 16;
        }
@@ -461,7 +461,7 @@
 
        while ((eva - va) >= (8 * 16)) {
                cache_r4k_op_8lines_16_4way(va, w2va, w3va, w4va,
-                   CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
+                   CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
                va   += (8 * 16);
                w2va += (8 * 16);
                w3va += (8 * 16);
@@ -469,10 +469,10 @@
        }
 
        while (va < eva) {
-               cache_op_r4k_line(va,   CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
-               cache_op_r4k_line(w2va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
-               cache_op_r4k_line(w3va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
-               cache_op_r4k_line(w4va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
+               cache_op_r4k_line(va,   CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+               cache_op_r4k_line(w2va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+               cache_op_r4k_line(w3va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+               cache_op_r4k_line(w4va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
                va   += 16;
                w2va += 16;
                w3va += 16;
@@ -501,14 +501,14 @@
 
        while ((eva - va) >= (16 * 32)) {
                cache_r4k_op_16lines_32_2way(va, w2va,
-                   CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
+                   CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
                va   += (16 * 32);
                w2va += (16 * 32);
        }
 
        while (va < eva) {
-               cache_op_r4k_line(va,   CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
-               cache_op_r4k_line(w2va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
+               cache_op_r4k_line(va,   CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+               cache_op_r4k_line(w2va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
                va   += 32;
                w2va += 32;
        }
@@ -541,7 +541,7 @@
 
        while ((eva - va) >= (8 * 32)) {
                cache_r4k_op_8lines_32_4way(va, w2va, w3va, w4va,
-                   CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
+                   CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
                va   += (8 * 32);
                w2va += (8 * 32);
                w3va += (8 * 32);
@@ -549,10 +549,10 @@
        }
 
        while (va < eva) {
-               cache_op_r4k_line(va,   CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
-               cache_op_r4k_line(w2va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
-               cache_op_r4k_line(w3va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
-               cache_op_r4k_line(w4va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
+               cache_op_r4k_line(va,   CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+               cache_op_r4k_line(w2va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+               cache_op_r4k_line(w3va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+               cache_op_r4k_line(w4va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
                va   += 32;
                w2va += 32;
                w3va += 32;
@@ -655,10 +655,10 @@
 
 #define        cache_r4k_op_32_4way_load_off(va1, va2, va3, va4, off, op)      \
 do {                                                                   \
-       cache_r4k_op_line_load_off((va ), (off), (op));                 \
+       cache_r4k_op_line_load_off((va1), (off), (op));                 \
        cache_r4k_op_line_load_off((va2), (off), (op));                 \
-       cache_r4k_op_line_load_off((va1), (off), (op));                 \
        cache_r4k_op_line_load_off((va3), (off), (op));                 \
+       cache_r4k_op_line_load_off((va4), (off), (op));                 \
 } while (/*CONSTCOND*/0)
 
 #define        cache_r4k_op_8lines_32_4way_load(va1, va2, va3, va4, op)        \
@@ -767,7 +767,7 @@
        s = splhigh();
        while ((eva - va) >= (8 * 32)) {
                cache_r4k_op_8lines_32_4way_load(va, w2va, w3va, w4va,
-                   CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
+                   CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
                va   += (8 * 32);
                w2va += (8 * 32);
                w3va += (8 * 32);
@@ -775,10 +775,10 @@
        }
 
        while (va < eva) {
-               cache_r4k_op_line_load(va,   CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
-               cache_r4k_op_line_load(w2va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
-               cache_r4k_op_line_load(w3va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
-               cache_r4k_op_line_load(w4va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
+               cache_r4k_op_line_load(va,   CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+               cache_r4k_op_line_load(w2va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+               cache_r4k_op_line_load(w3va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
+               cache_r4k_op_line_load(w4va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
                va   += 32;
                w2va += 32;
                w3va += 32;