[src/trunk]: src/sys/arch/sparc/sparc Mostly undo rev. 1.287: for modified pa...

[pk <pk%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b7349d821bfd
branches:  trunk
changeset: 565874:b7349d821bfd
user:      pk <pk%NetBSD.org@localhost>
date:      Thu Apr 22 10:14:58 2004 +0000

description:
Mostly undo rev. 1.287: for modified pages a table walk must be forced on
the next write access to get the modified bit set in the PTE and that
won't happen if it hits the cache.

diffstat:

 sys/arch/sparc/sparc/pmap.c |  21 +++++++++++++++++----
 1 files changed, 17 insertions(+), 4 deletions(-)

diffs (63 lines):

diff -r 34e6d906bbf9 -r b7349d821bfd sys/arch/sparc/sparc/pmap.c
--- a/sys/arch/sparc/sparc/pmap.c       Thu Apr 22 06:55:15 2004 +0000
+++ b/sys/arch/sparc/sparc/pmap.c       Thu Apr 22 10:14:58 2004 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.290 2004/04/19 15:20:42 pk Exp $ */
+/*     $NetBSD: pmap.c,v 1.291 2004/04/22 10:14:58 pk Exp $ */
 
 /*
  * Copyright (c) 1996
@@ -56,7 +56,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.290 2004/04/19 15:20:42 pk Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.291 2004/04/22 10:14:58 pk Exp $");
 
 #include "opt_ddb.h"
 #include "opt_kgdb.h"
@@ -837,7 +837,7 @@
                swap(vpte, swapval);
                tlb_flush_page(va, ctx, cpuset);
                oldval |= swapval;
-       } while (*vpte != 0);
+       } while (__predict_false(*vpte != 0));
 
        swapval = (oldval & ~bic) | bis;
        swap(vpte, swapval);
@@ -868,7 +868,7 @@
 #if defined(MULTIPROCESSOR)
        updatepte4m(va, ptep, 0xffffffff, pte, pageflush ? ctx : 0, cpuset);
 #else
-       if (pageflush)
+       if (__predict_true(pageflush))
                tlb_flush_page(va, ctx, 0);
        setpgt4m(ptep, pte);
 #endif /* MULTIPROCESSOR */
@@ -2710,6 +2710,7 @@
        int s;
        struct regmap *rp;
        struct segmap *sp;
+       int tpte;
 
        s = splvm();
        PMAP_HEAD_TO_MAP_LOCK();
@@ -2729,6 +2730,18 @@
                rp = &pm->pm_regmap[VA_VREG(va)];
                sp = &rp->rg_segmap[VA_VSEG(va)];
 
+               tpte = sp->sg_pte[VA_SUN4M_VPG(va)];
+               if ((tpte & SRMMU_TETYPE) == SRMMU_TEPTE ||
+                   (tpte & (SRMMU_PG_R|SRMMU_PG_M)) == 0)
+                       continue;
+
+               /*
+                * Flush cache if modified to make sure the pte M will be
+                * set again on the next write access.
+                */
+               if (pm->pm_ctx && (tpte & SRMMU_PG_M) == SRMMU_PG_M)
+                       cache_flush_page(va, pm->pm_ctxnum);
+
                flags |= MR4M(updatepte4m(va, &sp->sg_pte[VA_SUN4M_VPG(va)],
                                        SRMMU_PG_M | SRMMU_PG_R,
                                        0, pm->pm_ctxnum, PMAP_CPUSET(pm)));