[src/trunk]: src/sys/arch/mips/mips Make mips3_FlushICache() convert a0 into ...

[jeffs <jeffs%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/e4e499d8fd44
branches:  trunk
changeset: 495621:e4e499d8fd44
user:      jeffs <jeffs%NetBSD.org@localhost>
date:      Tue Aug 01 23:38:26 2000 +0000

description:
Make mips3_FlushICache() convert a0 into a KSEG0 + virtual index like
the _2way and mips3_FlushDCache(). This lets all mips3 cache ops accept
user virtual addresss w/o a tlb miss.  Since this is now done in both
ICache flush routines, no need to do it in pmap.c.  Fixed R4400
stability problems with setregs() cache flushing.

diffstat:

 sys/arch/mips/mips/locore_mips3.S |  9 +++++++--
 sys/arch/mips/mips/pmap.c         |  7 +++----
 2 files changed, 10 insertions(+), 6 deletions(-)

diffs (59 lines):

diff -r 1b8ebf97b12e -r e4e499d8fd44 sys/arch/mips/mips/locore_mips3.S
--- a/sys/arch/mips/mips/locore_mips3.S Tue Aug 01 23:19:21 2000 +0000
+++ b/sys/arch/mips/mips/locore_mips3.S Tue Aug 01 23:38:26 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore_mips3.S,v 1.43 2000/07/25 18:06:49 jeffs Exp $  */
+/*     $NetBSD: locore_mips3.S,v 1.44 2000/08/01 23:38:26 jeffs Exp $  */
 
 /*
  * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
@@ -1564,7 +1564,7 @@
  *             vaddr_t addr; vsize_t len;
  *
  *     Flush instruction cache for range of addr to addr + len - 1.
- *     The address can be any valid address so long as no TLB misses occur.
+ *     The address is reduced to a kseg0 index.
  *     Assumes a cache line size of 16 bytes for speed.
  *
  * Results:
@@ -1577,7 +1577,12 @@
  *----------------------------------------------------------------------------
  */
 LEAF(mips3_FlushICache)
+       lw      a2, mips_L1ICacheSize
+       addu    a2, -1
+       and     a0, a0, a2      # get index into primary cache
        addu    a1, 127         # Align
+       li      a2, MIPS_KSEG0_START
+       addu    a0, a0, a2
        srl     a1, a1, 7       # Number of unrolled loops
 1:
        cache   C_IINV_I, 0(a0)
diff -r 1b8ebf97b12e -r e4e499d8fd44 sys/arch/mips/mips/pmap.c
--- a/sys/arch/mips/mips/pmap.c Tue Aug 01 23:19:21 2000 +0000
+++ b/sys/arch/mips/mips/pmap.c Tue Aug 01 23:38:26 2000 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: pmap.c,v 1.104 2000/07/20 18:33:43 jeffs Exp $ */
+/*     $NetBSD: pmap.c,v 1.105 2000/08/01 23:38:26 jeffs Exp $ */
 
 /*-
  * Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -78,7 +78,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.104 2000/07/20 18:33:43 jeffs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.105 2000/08/01 23:38:26 jeffs Exp $");
 
 /*
  *     Manages physical address maps.
@@ -969,8 +969,7 @@
                printf("pmap_procwr: va %lx len %lx\n", va, len);
 #endif
                MachFlushDCache(va, len);
-               MachFlushICache(MIPS_PHYS_TO_KSEG0(va &
-                   (mips_L1ICacheSize - 1)), len);
+               MachFlushICache(va, len);
 #endif /* MIPS3 */
        } else {
 #ifdef MIPS1