[src/trunk]: src/sys/arch/mips/mips move TX39 specific cache configuration co...

[uch <uch%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/826c20b36222
branches:  trunk
changeset: 521418:826c20b36222
user:      uch <uch%NetBSD.org@localhost>
date:      Wed Jan 30 16:09:29 2002 +0000

description:
move TX39 specific cache configuration code to cache.c

diffstat:

 sys/arch/mips/mips/cache.c  |  24 +++++++++++++++++++++++-
 sys/arch/mips/mips/locore.S |  23 +----------------------
 2 files changed, 24 insertions(+), 23 deletions(-)

diffs (89 lines):

diff -r 1703a3711569 -r 826c20b36222 sys/arch/mips/mips/cache.c
--- a/sys/arch/mips/mips/cache.c        Wed Jan 30 15:16:06 2002 +0000
+++ b/sys/arch/mips/mips/cache.c        Wed Jan 30 16:09:29 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cache.c,v 1.8 2002/01/19 04:25:36 shin Exp $   */
+/*     $NetBSD: cache.c,v 1.9 2002/01/30 16:09:29 uch Exp $    */
 
 /*
  * Copyright 2001 Wasabi Systems, Inc.
@@ -114,6 +114,7 @@
 #include <mips/cache_tx39.h>
 void   tx3900_get_cache_config(void);
 void   tx3920_get_cache_config(void);
+void   tx39_cache_config_write_through(void);
 #endif /* ENABLE_MIPS_TX3900 */
 #endif /* MIPS1 */
 
@@ -277,6 +278,8 @@
 
                mips_pdcache_ways = 2;
                tx3900_get_cache_config();
+               /* change to write-through mode */
+               tx39_cache_config_write_through();
 
                uvmexp.ncolors = atop(mips_pdcache_size) / mips_pdcache_ways;
                break;
@@ -659,6 +662,25 @@
        if ((tx3900_cp0_config_read() & R3900_CONFIG_WBON) == 0)
                mips_pdcache_write_through = 1;
 }
+
+/*
+ * tx39_cache_config_write_through:
+ *
+ *     TX3922 write-through D-cache mode.
+ *     for TX3912, no meaning. (no write-back mode)
+ */
+void
+tx39_cache_config_write_through(void)
+{
+       u_int32_t r;
+
+       mips_dcache_wbinv_all();
+
+       __asm__ __volatile__("mfc0 %0, $3" : "=r"(r));
+       r &= 0xffffdfff;
+       __asm__ __volatile__("mtc0 %0, $3" : : "r"(r));
+}
+
 #endif /* ENABLE_MIPS_TX3900 */
 #endif /* MIPS1 */
 
diff -r 1703a3711569 -r 826c20b36222 sys/arch/mips/mips/locore.S
--- a/sys/arch/mips/mips/locore.S       Wed Jan 30 15:16:06 2002 +0000
+++ b/sys/arch/mips/mips/locore.S       Wed Jan 30 16:09:29 2002 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.130 2002/01/04 09:26:39 takemura Exp $    */
+/*     $NetBSD: locore.S,v 1.131 2002/01/30 16:09:29 uch Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -120,27 +120,6 @@
        la      gp, _C_LABEL(_gp)
 #endif
 
-#ifdef ENABLE_MIPS_TX3900
-       /*
-        * TX3922 write-through D-cache mode.
-        * for TX3912, no meaning. (no write-back mode)
-        */
-       mfc0    t0, R3900_COP_0_CONFIG
-       li      t1, 0xffffdfff
-       and     t0, t0, t1
-       mtc0    t0, R3900_COP_0_CONFIG
-       COP0_SYNC
-#ifdef R3900_CACHE_DISABLE
-       li      t0, ~(R3900_CONFIG_ICE|R3900_CONFIG_DCE)
-       mfc0    t1, R3900_COP_0_CONFIG
-       and     t1, t0, t1
-       nop
-       mtc0    t1, R3900_COP_0_CONFIG
-       COP0_SYNC
-       nop
-#endif /* R3900_CACHE_DISABLE */
-#endif /* ENABLE_MIPS_TX3900 */
-
 #ifdef NOFPU /* No FPU; avoid touching FPU registers */
        li      t0, 0                           # Disable interrupts and
        mtc0    t0, MIPS_COP_0_STATUS           # the fp coprocessor