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[src/nathanw_sa]: src/sys/arch/hpcsh/dev/hd64461 HD64461 video module.
details: https://anonhg.NetBSD.org/src/rev/9c30cd671e1b
branches: nathanw_sa
changeset: 504710:9c30cd671e1b
user: uch <uch%NetBSD.org@localhost>
date: Mon Jun 04 17:08:37 2001 +0000
description:
HD64461 video module.
diffstat:
sys/arch/hpcsh/dev/hd64461/hd64461reg.h | 137 +++++++++
sys/arch/hpcsh/dev/hd64461/hd64461videoreg.h | 404 +++++++++++++++++++++++++++
2 files changed, 541 insertions(+), 0 deletions(-)
diffs (truncated from 549 to 300 lines):
diff -r 3529906f2f78 -r 9c30cd671e1b sys/arch/hpcsh/dev/hd64461/hd64461reg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/hpcsh/dev/hd64461/hd64461reg.h Mon Jun 04 17:08:37 2001 +0000
@@ -0,0 +1,137 @@
+/* $NetBSD: hd64461reg.h,v 1.2.18.2 2001/06/04 17:08:37 uch Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by UCHIYAMA Yasushi.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define SH3_AREA4_BASE 0xb0000000
+#define SH3_AREA5_BASE 0xb4000000
+#define SH3_AREA6_BASE 0xb8000000
+
+/* HD64461 Address mapping (mapped to SH3 memory space) */
+
+/* SH3 Area 4 (Register, Framebuffer) */
+#define HD64461_REGBASE SH3_AREA4_BASE
+#define HD64461_REGSIZE 0x02000000
+#define HD64461_FBBASE (SH3_AREA4_BASE + 0x02000000)
+#define HD64461_FBSIZE 0x02000000
+#define HD64461_FBPAGESIZE 0x1000
+
+/* SH3 Area 5 (PCC1 memory space) */
+#define HD64461_PCC1_MEMBASE SH3_AREA5_BASE
+#define HD64461_PCC1_MEMSIZE 0x02000000
+
+/* SH3 Area 6 (PCC0 memory, I/O space*/
+#define HD64461_PCC0_MEMBASE SH3_AREA6_BASE
+#define HD64461_PCC0_MEMSIZE 0x02000000
+#define HD64461_PCC0_IOBASE (SH3_AREA6_BASE + 0x02000000)
+#define HD64461_PCC0_IOSIZE 0x02000000
+
+/*
+ * Register mapping.
+ */
+#define HD64461_SYSTEM_REGBASE 0xb0000000
+#define HD64461_SYSTEM_REGSIZE 0x00001000
+
+#define HD64461_LCDC_REGBASE 0xb0001000
+#define HD64461_LCDC_REGSIZE 0x00001000
+
+#define HD64461_PCMCIA_REGBASE 0xb0002000
+#define HD64461_PCMCIA_REGSIZE 0x00001000
+
+#define HD64461_AFE_REGBASE 0xb0003000
+#define HD64461_AFE_REGSIZE 0x00001000
+
+#define HD64461_GPIO_REGBASE 0xb0004000
+#define HD64461_GPIO_REGSIZE 0x00001000
+
+#define HD64461_INTC_REGBASE 0xb0005000
+#define HD64461_INTC_REGSIZE 0x00001000
+
+#define HD64461_TIMER_REGBASE 0xb0006000
+#define HD64461_TIMER_REGSIZE 0x00001000
+
+#define HD64461_IRDA_REGBASE 0xb0007000
+#define HD64461_IRDA_REGSIZE 0x00001000
+
+#define HD64461_UART_REGBASE 0xb0008000
+#define HD64461_UART_REGSIZE 0x00001000
+
+/*
+ * System Configuration Register and STANBY Mode
+ */
+/* Stanby Control Register */
+#define HD64461_SYSSTBCR_REG16 0xb0000000
+#define HD64461_SYSSTBCR_CKIO_STBY 0x2000
+#define HD64461_SYSSTBCR_SAFECKE_IST 0x1000
+#define HD64461_SYSSTBCR_SLCKE_IST 0x0800
+#define HD64461_SYSSTBCR_SAFECKE_OST 0x0400
+#define HD64461_SYSSTBCR_SLCKE_OST 0x0200
+#define HD64461_SYSSTBCR_SMIAST 0x0100
+#define HD64461_SYSSTBCR_SLCDST 0x0080
+#define HD64461_SYSSTBCR_SPC0ST 0x0040
+#define HD64461_SYSSTBCR_SPC1ST 0x0020
+#define HD64461_SYSSTBCR_SAFEST 0x0010
+#define HD64461_SYSSTBCR_STM0ST 0x0008
+#define HD64461_SYSSTBCR_STM1ST 0x0004
+#define HD64461_SYSSTBCR_SIRST 0x0002
+#define HD64461_SYSSTBCR_SURTSD 0x0001
+
+/* System Configuration Register */
+#define HD64461_SYSSYSCR_REG16 0xb0000002
+#define HD64461_SYSSYSCR_SCPU_BUS_IGAT 0x2000
+#define HD64461_SYSSYSCR_SPTA_IR 0x0080
+#define HD64461_SYSSYSCR_SPTA_TM 0x0040
+#define HD64461_SYSSYSCR_SPTB_UR 0x0020
+#define HD64461_SYSSYSCR_WAIT_CTL_SEL 0x0010
+#define HD64461_SYSSYSCR_SMODE1 0x0002
+#define HD64461_SYSSYSCR_SMODE0 0x0001
+
+/* CPU Data Bus Control Register */
+#define HD64461_SYSSCPUCR_REG16 0xb0000004
+#define HD64461_SYSSCPUCR_SPDSTOF 0x8000
+#define HD64461_SYSSCPUCR_SPDSTIG 0x4000
+#define HD64461_SYSSCPUCR_SPCSTOF 0x2000
+#define HD64461_SYSSCPUCR_SPCSTIG 0x1000
+#define HD64461_SYSSCPUCR_SPBSTOF 0x0800
+#define HD64461_SYSSCPUCR_SPBSTIG 0x0400
+#define HD64461_SYSSCPUCR_SPASTOF 0x0200
+#define HD64461_SYSSCPUCR_SPASTIG 0x0100
+#define HD64461_SYSSCPUCR_SLCDSTIG 0x0080
+#define HD64461_SYSSCPUCR_SCPU_CS56_EP 0x0040
+#define HD64461_SYSSCPUCR_SCPU_CMD_EP 0x0020
+#define HD64461_SYSSCPUCR_SCPU_ADDR_EP 0x0010
+#define HD64461_SYSSCPUCR_SCPDPU 0x0008
+#define HD64461_SYSSCPUCR_SCPU_A2319_EP 0x0001
diff -r 3529906f2f78 -r 9c30cd671e1b sys/arch/hpcsh/dev/hd64461/hd64461videoreg.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/hpcsh/dev/hd64461/hd64461videoreg.h Mon Jun 04 17:08:37 2001 +0000
@@ -0,0 +1,404 @@
+/* $NetBSD: hd64461videoreg.h,v 1.1.20.2 2001/06/04 17:08:37 uch Exp $ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by UCHIYAMA Yasushi.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * LCD Controller Control Register
+ */
+/* Base Address Register */
+#define HD64461_LCDCBAR_REG16 0xb0001000
+#define HD64461_LCDCBAR_MASK 0x3fff
+#define HD64461_LCDCBAR_SHIFT 12
+#define HD64461_LCDCBAR_BASEADDR(x) \
+ (((x) & HD64461_LCDCBAR_MASK) << HD64461_LCDCBAR_SHIFT)
+
+/* Line Address Offset Register */
+#define HD64461_LCDCLOR_REG16 0xb0001002
+#define HD64461_LCDCLOR_MASK 0x07ff
+#define HD64461_LCDCLOR(x) ((x) & HD64461_LCDCLOR_MASK)
+
+/* LCDC Control Register */
+#define HD64461_LCDCCR_REG16 0xb0001004
+#define HD64461_LCDCCR_STBAK 0x0400
+#define HD64461_LCDCCR_STREQ 0x0100
+#define HD64461_LCDCCR_MOFF 0x0080
+#define HD64461_LCDCCR_REFSEL 0x0040
+#define HD64461_LCDCCR_EPON 0x0020
+#define HD64461_LCDCCR_SPON 0x0010
+#define HD64461_LCDCCR_DSPSEL_MASK 0x7
+#define HD64461_LCDCCR_DSPSEL(x) ((x) & HD64461_LCDCCR_DSPSEL_MASK)
+#define HD64461_LCDCCR_DSPSEL_LCD_CRT 0x4
+#define HD64461_LCDCCR_DSPSEL_CRT 0x2
+#define HD64461_LCDCCR_DSPSEL_LCD 0x1
+
+/* LCD Display Register */
+/* 1 */
+#define HD64461_LCDLDR1_REG16 0xb0001010
+#define HD64461_LCDLDR1_DINV 0x0100
+#define HD64461_LCDLDR1_DON 0x0001
+/* 2 */
+#define HD64461_LCDLDR2_REG16 0xb0001012
+#define HD64461_LCDLDR2_CC1 0x0080
+#define HD64461_LCDLDR2_CC2 0x0040
+#define HD64461_LCDLDR2_LM_MASK 0x7
+#define HD64461_LCDLDR2_LM(x) ((x) & HD64461_LCDLDR2_LM_MASK)
+#define HD64461_LCDLDR2_LM_COLOR 0x4
+#define HD64461_LCDLDR2_LM_GRAY8 0x1
+#define HD64461_LCDLDR2_LM_GRAY4 0x0
+/* 3 */
+#define HD64461_LCDLDR3_REG16 0xb000101e
+#define HD64461_LCDLDR3_CS_SHIFT 5
+#define HD64461_LCDLDR3_CS_MASK 0x1f
+#define HD64461_LCDLDR3_CS(cr) \
+ (((cr) >> HD64461_LCDLDR3_CS_SHIFT) & \
+ HD64461_LCDLDR3_CS_MASK)
+#define HD64461_LCDLDR3_CS_SET(cr, val) \
+ ((cr) | (((val) << HD64461_LCDLDR3_CS_SHIFT) & \
+ (HD64461_LCDLDR3_CS_MASK << HD64461_LCDLDR3_CS_SHIFT)))
+#define HD64461_LCDLDR3_CG_MASK 0xf
+#define HD64461_LCDLDR3_CG(cr) \
+ ((cr) & HD64461_LCDLDR3_CG_MASK)
+#define HD64461_LCDLDR3_CG_CLR(cr) \
+ ((cr) & ~HD64461_LCDLDR3_CG_MASK)
+#define HD64461_LCDLDR3_CG_SET(cr, val) \
+ ((cr) | ((val) & HD64461_LCDLDR3_CG_MASK))
+
+/*
+ * select CL2 frequency
+ * 0x0 15 MHz (color) 15/2 (monochrome)
+ * 0x1 2.5 MHz
+ * 0x2 3.75 Mhz
+ * 0x4 5 Mhz
+ * 0x8 7.5 Mhz
+ * 0x10 10 Mhz
+ */
+#define HD64461_LCDLDR3_CG_COLOR16 0x8
+#define HD64461_LCDLDR3_CG_COLOR8 0x4
+#define HD64461_LCDLDR3_CG_GRAY6 0x3
+#define HD64461_LCDLDR3_CG_GRAY4 0x2
+#define HD64461_LCDLDR3_CG_GRAY2 0x1
+#define HD64461_LCDLDR3_CG_GRAY1 0x0
+
+/* LCD Number of Characters in Horizontal Register */
+#define HD64461_LCDLDHNCR_REG16 0xb0001014
+#define HD64461_LCDLDHNCR_NHD_SHIFT 8
+#define HD64461_LCDLDHNCR_NHD_MASK 0xff
+#define HD64461_LCDLDHNCR_NHD(cr) \
+ (((cr) >> HD64461_LCDLDHNCR_NHD_SHIFT) & \
+ HD64461_LCDLDHNCR_NHD_MASK)
+#define HD64461_LCDLDHNCR_NHD_SET(cr, val) \
+ ((cr) | (((val) << HD64461_LCDLDHNCR_NHD_SHIFT) & \
+ (HD64461_LCDLDHNCR_NHD_MASK << HD64461_LCDLDHNCR_NHD_SHIFT)))
+#define HD64461_LCDLDHNCR_NHT_SHIFT 0
+#define HD64461_LCDLDHNCR_NHT_MASK 0xff
+#define HD64461_LCDLDHNCR_NHT(cr) \
+ (((cr) >> HD64461_LCDLDHNCR_NHT_SHIFT) & \
+ HD64461_LCDLDHNCR_NHT_MASK)
+#define HD64461_LCDLDHNCR_NHT_SET(cr, val) \
+ ((cr) | (((val) << HD64461_LCDLDHNCR_NHT_SHIFT) & \
+ (HD64461_LCDLDHNCR_NHT_MASK << HD64461_LCDLDHNCR_NHT_SHIFT)))
+
+/* Start Position of Horizontal Register */
+#define HD64461_LCDLDHNSR_REG16 0xb0001016
+#define HD64461_LCDLDHNSR_HSW_SHIFT 8
+#define HD64461_LCDLDHNSR_HSW_MASK 0xf
+#define HD64461_LCDLDHNSR_HSW(cr) \
+ (((cr) >> HD64461_LCDLDHNSR_HSW_SHIFT) & \
+ HD64461_LCDLDHNSR_HSW_MASK)
+#define HD64461_LCDLDHNSR_HSW_SET(cr, val) \
+ ((cr) | (((val) << HD64461_LCDLDHNSR_HSW_SHIFT) & \
+ (HD64461_LCDLDHNSR_HSW_MASK << HD64461_LCDLDHNSR_HSW_SHIFT)))
+#define HD64461_LCDLDHNSR_HSP_SHIFT 0
+#define HD64461_LCDLDHNSR_HSP_MASK 0xff
+#define HD64461_LCDLDHNSR_HSP(cr) \
+ (((cr) >> HD64461_LCDLDHNSR_HSP_SHIFT) & \
+ HD64461_LCDLDHNSR_HSP_MASK)
+#define HD64461_LCDLDHNSR_HSP_SET(cr, val) \
+ ((cr) | (((val) << HD64461_LCDLDHNSR_HSP_SHIFT) & \
+ (HD64461_LCDLDHNSR_HSP_MASK << HD64461_LCDLDHNSR_HSP_SHIFT)))
+
+/* Total Vertical Lines Register */
+#define HD64461_LCDLDVNTR_REG16 0xb0001018
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