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[src/trunk]: src/sys/dev/pci New driver for the AMD PCnet-PCI family of Ether...
details: https://anonhg.NetBSD.org/src/rev/e0dd2c8bdd03
branches: trunk
changeset: 514287:e0dd2c8bdd03
user: thorpej <thorpej%NetBSD.org@localhost>
date: Mon Aug 27 19:42:18 2001 +0000
description:
New driver for the AMD PCnet-PCI family of Ethernet chips. This
driver uses direct DMA to mbufs (like other PCI network drivers,
and unlike the old "le at pci" driver), and also supports communication
with the MII-connected PHYs on the 10/100 boards.
diffstat:
sys/dev/pci/files.pci | 8 +-
sys/dev/pci/if_pcn.c | 2154 +++++++++++++++++++++++++++++++++++++++++++++++
sys/dev/pci/if_pcnreg.h | 76 +
3 files changed, 2237 insertions(+), 1 deletions(-)
diffs (truncated from 2260 to 300 lines):
diff -r 5577b8ab02f3 -r e0dd2c8bdd03 sys/dev/pci/files.pci
--- a/sys/dev/pci/files.pci Mon Aug 27 18:52:09 2001 +0000
+++ b/sys/dev/pci/files.pci Mon Aug 27 19:42:18 2001 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: files.pci,v 1.136 2001/08/22 00:36:57 thorpej Exp $
+# $NetBSD: files.pci,v 1.137 2001/08/27 19:42:19 thorpej Exp $
#
# Config file and device description for machine-independent PCI code.
# Included by ports that need it. Requires that the SCSI files be
@@ -125,6 +125,12 @@
attach le at pci with le_pci: le32
file dev/pci/if_le_pci.c le_pci
+# AMD PCnet-PCI Ethernet controller family
+# Supersedes if_le_pci.c
+device pcn: ether, ifnet, arp, mii
+attach pcn at pci
+file dev/pci/if_pcn.c pcn
+
# common code for siop/esiop pci front end
define siop_pci_common
file dev/pci/siop_pci_common.c siop_pci_common
diff -r 5577b8ab02f3 -r e0dd2c8bdd03 sys/dev/pci/if_pcn.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/dev/pci/if_pcn.c Mon Aug 27 19:42:18 2001 +0000
@@ -0,0 +1,2154 @@
+/* $NetBSD: if_pcn.c,v 1.1 2001/08/27 19:42:18 thorpej Exp $ */
+
+/*
+ * Copyright 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Device driver for the AMD PCnet-PCI series of Ethernet
+ * chips:
+ *
+ * * Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI
+ * Local Bus
+ *
+ * * Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller
+ * for PCI Local Bus
+ *
+ * * Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps
+ * Ethernet Controller for PCI Local Bus
+ *
+ * * Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller
+ * with OnNow Support
+ *
+ * * Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI
+ * Ethernet Controller with Integrated PHY
+ *
+ * This also supports the virtual PCnet-PCI Ethernet interface found
+ * in VMware.
+ *
+ * TODO:
+ *
+ * * Split this into bus-specific and bus-independent portions.
+ * The core could also be used for the ILACC (Am79900) 32-bit
+ * Ethernet chip (XXX only if we use an ILACC-compatible SWSTYLE).
+ */
+
+#include "bpfilter.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/callout.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/socket.h>
+#include <sys/ioctl.h>
+#include <sys/errno.h>
+#include <sys/device.h>
+#include <sys/queue.h>
+
+#include <uvm/uvm_extern.h> /* for PAGE_SIZE */
+
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_ether.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+
+#include <machine/bus.h>
+#include <machine/intr.h>
+#include <machine/endian.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include <dev/ic/am79900reg.h>
+#include <dev/ic/lancereg.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#include <dev/pci/if_pcnreg.h>
+
+/*
+ * Transmit descriptor list size. This is arbitrary, but allocate
+ * enough descriptors for 128 pending transmissions, and 4 segments
+ * per packet. This MUST work out to a power of 2.
+ *
+ * NOTE: We can't have any more than 512 Tx descriptors, SO BE CAREFUL!
+ *
+ * So we play a little trick here. We give each packet up to 8
+ * DMA segments, but only allocate 4 DMA segments per packet.
+ * The transmit logic can deal with this, we just are hoping to
+ * sneak by.
+ */
+#define PCN_NTXSEGS 8
+#define PCN_NTXSEGS_ALLOC 4
+
+#define PCN_TXQUEUELEN 128
+#define PCN_TXQUEUELEN_MASK (PCN_TXQUEUELEN - 1)
+#define PCN_NTXDESC (PCN_TXQUEUELEN * PCN_NTXSEGS_ALLOC)
+#define PCN_NTXDESC_MASK (PCN_NTXDESC - 1)
+#define PCN_NEXTTX(x) (((x) + 1) & PCN_NTXDESC_MASK)
+#define PCN_NEXTTXS(x) (((x) + 1) & PCN_TXQUEUELEN_MASK)
+
+/* Tx interrupt every N + 1 packets. */
+#define PCN_TXINTR_MASK 7
+
+/*
+ * Receive descriptor list size. We have one Rx buffer per incoming
+ * packet, so this logic is a little simpler.
+ */
+#define PCN_NRXDESC 128
+#define PCN_NRXDESC_MASK (PCN_NRXDESC - 1)
+#define PCN_NEXTRX(x) (((x) + 1) & PCN_NRXDESC_MASK)
+
+/*
+ * Control structures are DMA'd to the PCnet chip. We allocate them in
+ * a single clump that maps to a single DMA segment to make several things
+ * easier.
+ */
+struct pcn_control_data {
+ /* The transmit descriptors. */
+ struct letmd pcd_txdescs[PCN_NTXDESC];
+
+ /* The receive descriptors. */
+ struct lermd pcd_rxdescs[PCN_NRXDESC];
+
+ /* The init block. */
+ struct leinit pcd_initblock;
+};
+
+#define PCN_CDOFF(x) offsetof(struct pcn_control_data, x)
+#define PCN_CDTXOFF(x) PCN_CDOFF(pcd_txdescs[(x)])
+#define PCN_CDRXOFF(x) PCN_CDOFF(pcd_rxdescs[(x)])
+#define PCN_CDINITOFF PCN_CDOFF(pcd_initblock)
+
+/*
+ * Software state for transmit jobs.
+ */
+struct pcn_txsoft {
+ struct mbuf *txs_mbuf; /* head of our mbuf chain */
+ bus_dmamap_t txs_dmamap; /* our DMA map */
+ int txs_firstdesc; /* first descriptor in packet */
+ int txs_lastdesc; /* last descriptor in packet */
+};
+
+/*
+ * Software state for receive jobs.
+ */
+struct pcn_rxsoft {
+ struct mbuf *rxs_mbuf; /* head of our mbuf chain */
+ bus_dmamap_t rxs_dmamap; /* our DMA map */
+};
+
+/*
+ * Description of Rx FIFO watermarks for various revisions.
+ */
+const char *pcn_79c970_rcvfw[] = {
+ "16 bytes",
+ "64 bytes",
+ "128 bytes",
+ NULL,
+};
+
+const char *pcn_79c971_rcvfw[] = {
+ "16 bytes",
+ "64 bytes",
+ "112 bytes",
+ NULL,
+};
+
+/*
+ * Description of Tx start points for various revisions.
+ */
+const char *pcn_79c970_xmtsp[] = {
+ "8 bytes",
+ "64 bytes",
+ "128 bytes",
+ "248 bytes",
+};
+
+const char *pcn_79c971_xmtsp[] = {
+ "20 bytes",
+ "64 bytes",
+ "128 bytes",
+ "248 bytes",
+};
+
+const char *pcn_79c971_xmtsp_sram[] = {
+ "44 bytes",
+ "64 bytes",
+ "128 bytes",
+ "store-and-forward",
+};
+
+/*
+ * Description of Tx FIFO watermarks for various revisions.
+ */
+const char *pcn_79c970_xmtfw[] = {
+ "16 bytes",
+ "64 bytes",
+ "128 bytes",
+ NULL,
+};
+
+const char *pcn_79c971_xmtfw[] = {
+ "16 bytes",
+ "64 bytes",
+ "108 bytes",
+ NULL,
+};
+
+/*
+ * Software state per device.
+ */
+struct pcn_softc {
+ struct device sc_dev; /* generic device information */
+ bus_space_tag_t sc_st; /* bus space tag */
+ bus_space_handle_t sc_sh; /* bus space handle */
+ bus_dma_tag_t sc_dmat; /* bus DMA tag */
+ struct ethercom sc_ethercom; /* Ethernet common data */
+ void *sc_sdhook; /* shutdown hook */
+
+ /* Points to our media routines, etc. */
+ const struct pcn_variant *sc_variant;
+
+ void *sc_ih; /* interrupt cookie */
+
+ struct mii_data sc_mii; /* MII/media information */
+
+ struct callout sc_tick_ch; /* tick callout */
+
+ bus_dmamap_t sc_cddmamap; /* control data DMA map */
+#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
+
+ /* Software state for transmit and receive descriptors. */
+ struct pcn_txsoft sc_txsoft[PCN_TXQUEUELEN];
+ struct pcn_rxsoft sc_rxsoft[PCN_NRXDESC];
+
+ /* Control data structures */
+ struct pcn_control_data *sc_control_data;
+#define sc_txdescs sc_control_data->pcd_txdescs
+#define sc_rxdescs sc_control_data->pcd_rxdescs
+#define sc_initblock sc_control_data->pcd_initblock
+
+#ifdef PCN_EVENT_COUNTERS
+ /* Event counters. */
+ struct evcnt sc_ev_txsstall; /* Tx stalled due to no txs */
+ struct evcnt sc_ev_txdstall; /* Tx stalled due to no txd */
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