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[src/trunk]: src/share/man/man4 Import hp700 / hppa specific man pages from O...



details:   https://anonhg.NetBSD.org/src/rev/3b01a640afc1
branches:  trunk
changeset: 570080:3b01a640afc1
user:      jkunz <jkunz%NetBSD.org@localhost>
date:      Wed Sep 22 16:38:26 2004 +0000

description:
Import hp700 / hppa specific man pages from OpenBSD.

diffstat:

 share/man/man4/man4.hp700/Makefile    |   11 +
 share/man/man4/man4.hp700/asp.4       |  104 ++++++++++++
 share/man/man4/man4.hp700/cpu.4       |  266 +++++++++++++++++++++++++++++++
 share/man/man4/man4.hp700/dino.4      |  103 ++++++++++++
 share/man/man4/man4.hp700/gsc.4       |  118 ++++++++++++++
 share/man/man4/man4.hp700/gsckbc.4    |   77 +++++++++
 share/man/man4/man4.hp700/harmony.4   |  116 +++++++++++++
 share/man/man4/man4.hp700/intro.4     |  286 ++++++++++++++++++++++++++++++++++
 share/man/man4/man4.hp700/io.4        |  156 ++++++++++++++++++
 share/man/man4/man4.hp700/lasi.4      |  148 +++++++++++++++++
 share/man/man4/man4.hp700/mem.4       |   84 +++++++++
 share/man/man4/man4.hp700/mongoose.4  |   83 +++++++++
 share/man/man4/man4.hp700/phantomas.4 |   87 ++++++++++
 share/man/man4/man4.hp700/wax.4       |  107 ++++++++++++
 share/man/man4/sti.4                  |  270 ++++++++++++++++++++++++++++++++
 15 files changed, 2016 insertions(+), 0 deletions(-)

diffs (truncated from 2076 to 300 lines):

diff -r 5aa0d96a18b4 -r 3b01a640afc1 share/man/man4/man4.hp700/Makefile
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/share/man/man4/man4.hp700/Makefile        Wed Sep 22 16:38:26 2004 +0000
@@ -0,0 +1,11 @@
+#      $NetBSD: Makefile,v 1.1 2004/09/22 16:38:26 jkunz Exp $
+#      from: @(#)Makefile      8.1 (Berkeley) 6/18/93
+
+MAN=   asp.4 cpu.4 dino.4 gsc.4 gsckbc.4 harmony.4 intro.4 io.4 lasi.4 \
+       mem.4 mongoose.4 phantomas.4 wax.4
+
+USETBL=
+
+MANSUBDIR=/hp700
+
+.include <bsd.man.mk>
diff -r 5aa0d96a18b4 -r 3b01a640afc1 share/man/man4/man4.hp700/asp.4
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/share/man/man4/man4.hp700/asp.4   Wed Sep 22 16:38:26 2004 +0000
@@ -0,0 +1,104 @@
+.\"    $NetBSD: asp.4,v 1.1 2004/09/22 16:38:26 jkunz Exp $
+.\"
+.\"    $OpenBSD: asp.4,v 1.15 2003/08/31 20:53:33 jmc Exp $
+.\"
+.\" Copyright (c) 1999 Michael Shalayeff
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.Dd April 1, 1999
+.Dt ASP 4 hp700
+.Os
+.Sh NAME
+.Nm asp
+.Nd first generation I/O subsystem
+.Sh SYNOPSIS
+.Cd "asp*    at mainbus0"
+.Cd "gsc*    at asp?"
+.Sh DESCRIPTION
+Core bus controller and I/O subsystem as present on older HP 9000/700
+workstations.
+The supported core bus controllers are those used in conjunction with
+.Tn PA7000 ,
+.Tn PA7100 ,
+and
+.Tn PA7150
+CPUs and include:
+.Pp
+.Bl -bullet -compact
+.It
+Core bus controller
+.It
+System Clock
+.It
+Interrupt Controller
+.It
+DMA Controller
+.It
+Real Time Clock Interface
+.It
+RAM and EEPROM controllers
+.El
+.Sh MACHINES
+An incomplete list of machines that use the
+.Tn ASP
+bus controller:
+.Pp
+.Bl -bullet -compact
+.It
+705, 710
+.It
+715/{33,50,75}
+.It
+725/{50,75}
+.It
+720, 730, 750
+.It
+735/*
+.It
+742i
+.It
+745i/{50,75}
+.It
+747i/{50,75}
+.It
+755/*
+.El
+.Sh SEE ALSO
+.Xr gsc 4 ,
+.Xr intro 4 ,
+.Xr io 4
+.Rs
+.%T "Hardball I/O Subsystem ERS"
+.%N Revision 1.1
+.%D 30 September 1991
+.%Q Hewlett-Packard
+.Re
+.Sh HISTORY
+The
+.Nm
+driver
+appeared in
+.Ox 2.4 .
+It was ported to
+.Nx 1.6
+by Matthew Fredette.
diff -r 5aa0d96a18b4 -r 3b01a640afc1 share/man/man4/man4.hp700/cpu.4
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/share/man/man4/man4.hp700/cpu.4   Wed Sep 22 16:38:26 2004 +0000
@@ -0,0 +1,266 @@
+.\"    $NetBSD: cpu.4,v 1.1 2004/09/22 16:38:26 jkunz Exp $
+.\"
+.\" $OpenBSD: cpu.4tbl,v 1.19 2004/04/08 16:17:09 mickey Exp $
+.\"
+.\" Copyright (c) 2002 Michael Shalayeff
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+.\" IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
+.\" INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+.\" (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+.\" SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+.\" STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+.\" IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+.\" THE POSSIBILITY OF SUCH DAMAGE.
+.\"
+.Dd April 4, 2002
+.Dt CPU 4 hp700
+.Os
+.Sh NAME
+.Nm cpu
+.Nd HP PA-RISC CPU
+.Sh SYNOPSIS
+.Cd "cpu*       at mainbus0 irq 31
+.Sh DESCRIPTION
+The following table lists the
+.Tn PA-RISC
+CPU types and their characteristics, such as TLB, maximum
+cache sizes and
+.Tn HP 9000/700
+machines they were used in (see also
+.Xr intro 4
+for the reverse list).
+.Pp
+.in +\n(dIu
+.TS
+.\" tab (:) ;
+l l l l l l l
+l l l l l l l
+l l l l l l l
+_ _ _ _ _ _ _
+l l l l l l l .
+CPU:PA:Clock:Caches:TLB:BTLB:Models
+   :  :(max):(max) :   :    :
+   :  : MHz : KB   :   :    :
+7000:1.1a:66 : 256 L1I:96I:4 I:705,710,720
+    :    :   : 256 L1D:96D:4 D:730,750
+7100:1.1b:100:1024 L1I:120:16:715/33/50/75
+    :    :   :2048 L1D:   :  :725/50/75
+    :    :   :        :   :  :{735,755}/100
+    :    :   :        :   :  :742i, 745i, 747i
+7150:1.1b:125:1024 L1I:120:16:{735,755}/125
+    :    :   :2048 L1D:   :  :
+7100LC:1.1c:100:   1 L1I:64:8:712/60/80/100
+      :    :   :1024 L2I:  : :715/64/80/100
+      :    :   :1024 L2D:  : :715/100XC
+      :    :   :        :  : :725/64/100
+      :    :   :        :  : :743i, 748i
+      :    :   :        :  : :SAIC
+7200:1.1d:140:   2 L1 :120:16:C100,C110
+    :    :   :1024 L2I:   :  :J200,J210
+    :    :   :1024 L2D:   :  :
+7300LC:1.1e:180:  64 L1I:96:8:A180,A180C
+       :    :  :  64 L1D:  : :B132,B160,B180
+       :    :  :8192 L2:  : :C132L,C160L
+       :    :  :       :  : :744, 745, 748
+       :    :  :       :  : :RDI PrecisioBook
+.TE
+.in -\n(dIu
+.Sh FLOATING-POINT COPROCESSOR
+The following table summarizes available floating-point coprocessor
+models for the 32-bit
+.Tn PA-RISC
+processors.
+.Pp
+.in +\n(dIu
+.TS
+tab (:) ;
+l l
+_ _
+l l .
+FPU:Model
+Indigo:
+Sterling I MIU (TYCO):
+Sterling I MIU (ROC w/Weitek):
+FPC (w/Weitek):
+FPC (w/Bit):
+Timex-II:
+Rolex:725/50, 745i
+HARP-I:
+Tornado:J2x0,C1x0
+PA-50 (Hitachi):
+PCXL:712/60/80/100
+.TE
+.in -\n(dIu
+.Sh SUPERSCALAR EXECUTION
+The following table summarizes the superscalar execution capabilities
+of 32-bit
+.Tn PA-RISC
+processors.
+.Pp
+.in +\n(dIu
+.TS
+nokeep tab (:) ;
+l l l
+_ _ _
+l l l .
+CPU:Units:Bundles
+7100:1 integer ALU:load-store/fp
+    :1 FP         :int/fp
+    :             :branch/*
+7100LC:2 integer ALU:load-store/int
+      :1 FP        :load-store/fp
+      :             :int/fp
+      :             :branch/*
+7200:2 integer ALU:load-store/int
+    :1 FP         :load-store/fp
+    :        :int/int
+    :        :int/fp
+    :        :branch/*
+7300LC:2 integer ALU:load-store/int
+      :1 FP         :load-store/fp
+      :        :int/fp
+      :        :branch/*
+.TE
+.in -\n(dIu
+.Pp
+In conclusion, all of the above CPUs are dual-issue, or 2-way superscalar,
+with the exception that on CPUs with two integer ALUs only one of these
+units is capable of doing shift, load/store, and test operations.
+Additionally, there are several kinds of restrictions placed upon the
+superscalar execution:
+.Pp
+For the purpose of showing which instructions are allowed to proceed
+together through the pipeline, they are divided into classes:
+.Pp
+.in +\n(dIu
+.TS
+tab (:) ;
+l l
+_ _
+l l .
+Class:Description
+flop:floating point operation
+ldst:loads and stores
+flex:integer ALU
+mm:shifts, extracts and deposits
+nul:might nullify successor
+bv:BV, BE
+br:other branches
+fsys:FTEST and FP status/exception
+sys:system control instructions
+.TE
+.in -\n(dIu
+.Pp
+For CPUs with two integer ALUs (7100LC, 7200, 7300LC), the following
+table lists the instructions which are allowed to be executed
+concurrently:
+.Pp
+.in +\n(dIu
+.TS



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