[src/trunk]: src/sys/dev/pci On Rhine III, don't set VR_EECSR_LOAD before rea...

[scw <scw%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/489708517934
branches:  trunk
changeset: 555302:489708517934
user:      scw <scw%NetBSD.org@localhost>
date:      Thu Nov 13 22:29:09 2003 +0000

description:
On Rhine III, don't set VR_EECSR_LOAD before reading the MAC address.
This reloads the entire EEPROM, not just the MAC address, which can
cause problems for the host PCI bus under certain circumstances. The
chip already loads the EEPROM at powerup/reset anyway.

XXX: This probably applies to the other Rhine variants too, but I don't
have a data sheet to confirm this behaviour.

diffstat:

 sys/dev/pci/if_vr.c |  20 ++++++++++++++++----
 1 files changed, 16 insertions(+), 4 deletions(-)

diffs (42 lines):

diff -r 9ed4433da980 -r 489708517934 sys/dev/pci/if_vr.c
--- a/sys/dev/pci/if_vr.c       Thu Nov 13 22:18:10 2003 +0000
+++ b/sys/dev/pci/if_vr.c       Thu Nov 13 22:29:09 2003 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: if_vr.c,v 1.65 2003/10/17 17:42:35 tsutsui Exp $       */
+/*     $NetBSD: if_vr.c,v 1.66 2003/11/13 22:29:09 scw Exp $   */
 
 /*-
  * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
@@ -104,7 +104,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.65 2003/10/17 17:42:35 tsutsui Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_vr.c,v 1.66 2003/11/13 22:29:09 scw Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -1563,9 +1563,21 @@
         * they've been programmed a special way. Consequently,
         * we need to read the node address from the PAR0 and PAR1
         * registers.
+        *
+        * XXXSCW: On the Rhine III, setting VR_EECSR_LOAD forces a reload
+        *         of the *whole* EEPROM, not just the MAC address. This is
+        *         pretty pointless since the chip does this automatically
+        *         at powerup/reset.
+        *         I suspect the same thing applies to the other Rhine
+        *         variants, but in the absence of a data sheet for those
+        *         (and the lack of anyone else noticing the problems this
+        *         causes) I'm going to retain the old behaviour for the
+        *         other parts.
         */
-       VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
-       DELAY(200);
+       if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_VIATECH_VT6105) {
+               VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
+               DELAY(200);
+       }
        for (i = 0; i < ETHER_ADDR_LEN; i++)
                eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);