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[src/trunk]: src/sys/arch/sparc64 Overhaul cache flush code and coredump code.
details: https://anonhg.NetBSD.org/src/rev/6f1cd5021259
branches: trunk
changeset: 495590:6f1cd5021259
user: eeh <eeh%NetBSD.org@localhost>
date: Tue Aug 01 00:40:15 2000 +0000
description:
Overhaul cache flush code and coredump code.
diffstat:
sys/arch/sparc64/include/kcore.h | 37 +-
sys/arch/sparc64/sparc64/locore.s | 414 +++++++++++++++++++++++-------------
sys/arch/sparc64/sparc64/machdep.c | 58 ++++-
sys/arch/sparc64/sparc64/pmap.c | 190 ++--------------
4 files changed, 365 insertions(+), 334 deletions(-)
diffs (truncated from 1103 to 300 lines):
diff -r f70288d53f9d -r 6f1cd5021259 sys/arch/sparc64/include/kcore.h
--- a/sys/arch/sparc64/include/kcore.h Tue Aug 01 00:36:05 2000 +0000
+++ b/sys/arch/sparc64/include/kcore.h Tue Aug 01 00:40:15 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: kcore.h,v 1.3 1998/08/13 02:10:44 eeh Exp $ */
+/* $NetBSD: kcore.h,v 1.4 2000/08/01 00:40:26 eeh Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@@ -40,23 +40,28 @@
* The layout of a kernel core on the dump device is as follows:
* a `struct kcore_seg' of type CORE_CPU
* a `struct cpu_kcore_hdr'
- * an array of `cpu_kcore_hdr.nmemseg' phys_ram_seg_t's
- * an array of `cpu_kcore_hdr.nsegmap' segmap structures
- * an array of `cpu_kcore_hdr.npmegs' PTEs (zero of these on sun4ms).
*/
typedef struct cpu_kcore_hdr {
- int cputype; /* CPU type associated with this dump */
- u_long kernbase; /* copy of KERNBASE goes here */
- int nmemseg; /* # of physical memory segments */
- u_long memsegoffset; /* start of memseg array (relative */
+ int cputype; /* CPU type associated with this dump */
+
+ int nmemseg; /* # of physical memory segments */
+ uint64_t memsegoffset; /* start of memseg array (relative */
+ /* to the start of this header) */
+
+ int nsegmap; /* # of kernel segs */
+ uint64_t segmapoffset; /* start of segmap array (relative */
/* to the start of this header) */
- int nsegmap; /* # of segmaps following */
- u_long segmapoffset; /* start of segmap array (relative */
- /* to the start of this header) */
- int npmeg; /* # of PMEGs; [sun4/sun4c] only */
- u_long pmegoffset; /* start of pmeg array (relative */
- /* to the start of this header) */
-/* SPARC64 stuff */
- paddr_t kphys; /* Physical address of 4MB locked TLB */
+
+ uint64_t kernbase; /* copy of KERNBASE goes here */
+ uint64_t cpubase; /* Pointer to cpu_info structure */
+
+ uint64_t ktextbase; /* Virtual start of text segment */
+ uint64_t ktextp; /* Physical address of 4MB locked TLB */
+ uint64_t ktextsz; /* Size of locked kernel text segment. */
+
+ uint64_t kdatabase; /* Virtual start of data segment */
+ uint64_t kdatap; /* Physical address of 4MB locked TLB */
+ uint64_t kdatasz; /* Size of locked kernel data segment. */
+
} cpu_kcore_hdr_t;
diff -r f70288d53f9d -r 6f1cd5021259 sys/arch/sparc64/sparc64/locore.s
--- a/sys/arch/sparc64/sparc64/locore.s Tue Aug 01 00:36:05 2000 +0000
+++ b/sys/arch/sparc64/sparc64/locore.s Tue Aug 01 00:40:15 2000 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: locore.s,v 1.90 2000/07/25 15:15:32 pk Exp $ */
+/* $NetBSD: locore.s,v 1.91 2000/08/01 00:40:15 eeh Exp $ */
/*
* Copyright (c) 1996-1999 Eduardo Horvath
* Copyright (c) 1996 Paul Kranenburg
@@ -224,6 +224,23 @@
/*
+ * Combine 2 regs -- used to convert 64-bit ILP32
+ * values to LP64.
+ */
+#define COMBINE(r1, r2, d) \
+ sllx r1, 32, d; \
+ or d, r2, d
+
+/*
+ * Split 64-bit value in 1 reg into high and low halves.
+ * Used for ILP32 return values.
+ */
+#define SPLIT(r0, r1) \
+ srl r0, 0, r1; \
+ srlx r0, 32, r0
+
+
+/*
* A handy macro for maintaining instrumentation counters.
* Note that this clobbers %o0 and %o1. Normal usage is
* something like:
@@ -2942,7 +2959,8 @@
set CPCB, %g6 ! Load up nsaved
LDPTR [%g6], %g6
- ldub [%g6 + PCB_NSAVED], %g6
+ clr %g6
+! ldub [%g6 + PCB_NSAVED], %g6! this could fault
sllx %g6, 9, %g6
or %g6, %g4, %g4
@@ -4191,6 +4209,11 @@
wr %g0, 1, CLEAR_SOFTINT
DLFLUSH(%g3, %g2)
#ifndef TICK_IS_TIME
+ rd TICK_CMPR, %g2
+ rd %tick, %g5
+ srax %g2, 1, %g2
+ cmp %g2, %g5
+ tg %xcc, 1
wrpr %g0, 0, %tick ! Reset %tick so we'll get another interrupt
#endif
ba,pt %icc, setup_sparcintr
@@ -6110,11 +6133,42 @@
flush %o2
retl
wrpr %o3, %pstate
-/*
- * dcache_flush_page()
- *
- * Clear one page from D$. We should do one for the I$,
- * but it does not alias and is not likely as large a problem.
+
+
+/*
+ * blast_icache()
+ *
+ * Clear out all of I$ regardless of contents
+ * Does not modify %o0
+ *
+ */
+ .align 8
+ .globl _C_LABEL(blast_icache)
+ .proc 1
+ FTYPE(blast_icache)
+_C_LABEL(blast_icache):
+/*
+ * We turn off interrupts for the duration to prevent RED exceptions.
+ */
+ rdpr %pstate, %o3
+ set (2*NBPG)-8, %o1
+ andn %o3, PSTATE_IE, %o4 ! Turn off PSTATE_IE bit
+ wrpr %o4, 0, %pstate
+1:
+ stxa %g0, [%o1] ASI_ICACHE_TAG
+ brnz,pt %o1, 1b
+ dec 8, %o1
+ sethi %hi(KERNBASE), %o2
+ flush %o2
+ retl
+ wrpr %o3, %pstate
+
+
+
+/*
+ * dcache_flush_page(vaddr_t pa)
+ *
+ * Clear one page from D$ and I$.
*
*/
.align 8
@@ -6122,28 +6176,185 @@
.proc 1
FTYPE(dcache_flush_page)
_C_LABEL(dcache_flush_page):
- mov -1, %g1 ! Generate mask for tag: bits [29..2]
- srlx %o0, 13-2, %g2 ! Tag is VA bits <40:13> in bits <29:2>
- srl %g1, 2, %g1 ! Now we have bits <29:0> set
- andn %g1, 3, %g1 ! Now we have bits <29:2> set
-
- set (2*NBPG), %o3
- clr %o1
-1:
- ldxa [%o1] ASI_DCACHE_TAG, %g3
- xor %g3, %g2, %g3
- andcc %g3, %g1, %g0
+#ifdef _LP64
+ COMBINE(%o0, %o1, %o0)
+#endif
+
+ !! Try using cache_flush_phys for a change.
+
+ mov -1, %o1 ! Generate mask for tag: bits [29..2]
+ srlx %o0, 13-2, %o2 ! Tag is VA bits <40:13> in bits <29:2>
+ srl %o1, 2, %o1 ! Now we have bits <29:0> set
+ andn %o1, 3, %o1 ! Now we have bits <29:2> set
+
+ set (2*NBPG), %o5
+ clr %o4
+1:
+ ldxa [%o4] ASI_DCACHE_TAG, %o3
+ xor %o3, %o2, %o3
+ andcc %o3, %o1, %g0
+ bne,pt %xcc, 2f
+ dec 16, %o5
+ membar #LoadStore
+ stxa %g0, [%o4] ASI_DCACHE_TAG
+ membar #StoreLoad
+2:
+ brnz,pt %o5, 1b
+ inc 16, %o4
+
+ !! Now do the I$
+ mov -1, %o1 ! Generate mask for tag: bits [35..8]
+ srlx %o0, 13-8, %o2
+ srl %o1, 32-35+7, %o1
+ sll %o1, 7, %o1 ! Mask
+
+ set (2*NBPG), %o5
+ clr %o4
+1:
+ ldda [%o4] ASI_ICACHE_TAG, %g0 ! Tag goes in %g1
+ xor %g1, %o2, %g1
+ andcc %g1, %o1, %g0
bne,pt %xcc, 2f
- dec 16, %o3
- stxa %g0, [%o1] ASI_DCACHE_TAG
+ dec 16, %o5
+ membar #LoadStore
+ stxa %g0, [%o4] ASI_ICACHE_TAG
+ membar #StoreLoad
2:
- brnz,pt %o3, 1b
- inc 16, %o1
+ brnz,pt %o5, 1b
+ inc 16, %o4
+
+ sethi %hi(KERNBASE), %o5
+ flush %o5
+ membar #Sync
+ retl
+ nop
+
+/*
+ * cache_flush_virt(va, len)
+ *
+ * Clear everything in that va range from D$ and I$.
+ *
+ */
+ .align 8
+ .globl _C_LABEL(cache_flush_virt)
+ .proc 1
+ FTYPE(cache_flush_virt)
+_C_LABEL(cache_flush_virt):
+ brz,pn %o1, 2f ! What? nothing to clear?
+ add %o0, %o1, %o2
+ mov 0x1ff, %o3
+ sllx %o3, 5, %o3 ! Generate mask for VA bits
+ and %o0, %o3, %o0
+ and %o2, %o3, %o2
+ sub %o2, %o1, %o4 ! End < start? need to split flushes.
+ sethi %hi((1<<13)), %o5
+ brlz,pn %o4, 1f
+ movrz %o4, %o3, %o4 ! If start == end we need to wrap
+
+ !! Clear from start to end
+1:
+ stxa %g0, [%o0] ASI_DCACHE_TAG
+ dec 16, %o4
+ xor %o5, %o0, %o3 ! Second way
+ stxa %g0, [%o0] ASI_ICACHE_TAG
+ stxa %g0, [%o3] ASI_ICACHE_TAG
+ brgz,pt %o4, 1b
+ inc 16, %o0
+2:
sethi %hi(KERNBASE), %o5
flush %o5
+ membar #Sync
retl
nop
+ !! We got a hole. Clear from start to hole
+ clr %o4
+3:
+ stxa %g0, [%o4] ASI_DCACHE_TAG
+ dec 16, %o1
+ xor %o5, %o4, %g1 ! Second way
+ stxa %g0, [%o4] ASI_ICACHE_TAG
+ stxa %g0, [%g1] ASI_ICACHE_TAG
+ brgz,pt %o1, 3b
+ inc 16, %o4
+
+ !! Now clear to the end.
+ sub %o3, %o2, %o4 ! Size to clear (NBPG - end)
+ ba,pt %icc, 1b
+ mov %o2, %o0 ! Start of clear
+
+/*
+ * cache_flush_phys __P((paddr_t, psize_t, int));
+ *
+ * Clear a set of paddrs from the D$, I$ and if param3 is
+ * non-zero, E$. (E$ is not supported yet).
+ */
+
+ .align 8
+ .globl _C_LABEL(cache_flush_phys)
+ .proc 1
+ FTYPE(cache_flush_phys)
+_C_LABEL(cache_flush_phys):
+#ifndef _LP64
+ COMBINE(%o0, %o1, %o0)
+ COMBINE(%o2, %o3, %o1)
+ mov %o4, %o2
+#endif
+#ifdef DEBUG
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