[src/trunk]: src/sys/arch/mips/alchemy Add a bus_space that makes use of wire...

[gdamore <gdamore%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/09b8c23cbc5a
branches:  trunk
changeset: 588046:09b8c23cbc5a
user:      gdamore <gdamore%NetBSD.org@localhost>
date:      Mon Feb 06 03:07:44 2006 +0000

description:
Add a bus_space that makes use of wired TLB entries, as required for PCI,
PCMCIA, and perhaps other devices on Alchemy parts.

Closes PR port-evbmips/32298
Reviewed as part of PCI changes by matt@, izumi@, and probably also simonb@.

This implementation has been tested seperately with my PCI code.  This commit
does not add the necessary changes to configuration files to include this in
current configurations yet, as I intend to add that when I add the
multi-platform configuration support for evbmips/alchemy (which will be
required for PCI anyway.)

diffstat:

 sys/arch/mips/alchemy/au_wired_space.c         |  749 +++++++++++++++++++++++++
 sys/arch/mips/alchemy/include/au_wired_space.h |   50 +
 2 files changed, 799 insertions(+), 0 deletions(-)

diffs (truncated from 807 to 300 lines):

diff -r 695175964ec1 -r 09b8c23cbc5a sys/arch/mips/alchemy/au_wired_space.c
--- /dev/null   Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/mips/alchemy/au_wired_space.c    Mon Feb 06 03:07:44 2006 +0000
@@ -0,0 +1,749 @@
+/* $NetBSD: au_wired_space.c,v 1.1 2006/02/06 03:07:44 gdamore Exp $ */
+
+/*-
+ * Copyright (c) 2006 Itronix Inc.
+ * All rights reserved.
+ *
+ * Written by Garrett D'Amore for Itronix Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of Itronix Inc. may not be used to endorse
+ *    or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */ 
+/*
+ * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
+ * Simulation Facility, NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *     This product includes software developed by the NetBSD
+ *     Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: au_wired_space.c,v 1.1 2006/02/06 03:07:44 gdamore Exp $");
+
+/*
+ * This provides mappings for the upper I/O regions used on some
+ * Alchemy parts, e.g. PCI and PCMCIA spaces.  These spaces require
+ * the use of wired TLB entries.
+ *
+ * Earlier Alchemy parts with all of peripherials located in the
+ * bottom 4GB of physical memory, do not need this.
+ */
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/extent.h>
+#include <sys/malloc.h>
+#include <sys/endian.h>
+
+#include <machine/bus.h>
+#include <machine/locore.h>
+#include <machine/wired_map.h>
+#include <mips/alchemy/include/au_wired_space.h>
+
+#ifndef        AU_WIRED_EXTENT_SZ
+#define        AU_WIRED_EXTENT_SZ      EXTENT_FIXED_STORAGE_SIZE(10)
+#endif
+
+typedef struct au_wired_cookie {
+       const char      *c_name;
+       bus_addr_t      c_start;
+       bus_size_t      c_size;
+       paddr_t         c_pbase;
+       int             c_flags;
+       int             c_swswap;
+       boolean_t       c_hwswap;
+       struct extent   *c_extent;
+       long            c_exstore[AU_WIRED_EXTENT_SZ/sizeof (long)];
+} au_wired_cookie_t;
+
+int au_wired_map(void *, bus_addr_t, bus_size_t, int,
+    bus_space_handle_t *, int);
+void au_wired_unmap(void *, bus_space_handle_t, bus_size_t, int);
+void *au_wired_vaddr(void *, bus_space_handle_t);
+int au_wired_subregion(void *, bus_space_handle_t, bus_size_t, bus_size_t,
+    bus_space_handle_t *);
+paddr_t au_wired_mmap(void *, bus_addr_t, off_t, int, int);
+int au_wired_alloc(void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t,
+    bus_size_t, int, bus_addr_t *, bus_space_handle_t *);
+void au_wired_free(void *, bus_space_handle_t, bus_size_t);
+void au_wired_barrier(void *, bus_space_handle_t, bus_size_t, bus_size_t, int);
+uint8_t au_wired_r_1(void *, bus_space_handle_t, bus_size_t);
+uint16_t au_wired_r_2(void *, bus_space_handle_t, bus_size_t);
+uint32_t au_wired_r_4(void *, bus_space_handle_t, bus_size_t);
+uint64_t au_wired_r_8(void *, bus_space_handle_t, bus_size_t);
+void au_wired_rm_1(void *, bus_space_handle_t, bus_size_t, uint8_t *,
+    bus_size_t);
+void au_wired_rm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *,
+    bus_size_t);
+void au_wired_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *,
+    bus_size_t);
+void au_wired_rm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *,
+    bus_size_t);
+void au_wired_rr_1(void *, bus_space_handle_t, bus_size_t, uint8_t *,
+    bus_size_t);
+void au_wired_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *,
+    bus_size_t);
+void au_wired_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *,
+    bus_size_t);
+void au_wired_rr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *,
+    bus_size_t);
+void au_wired_w_1(void *, bus_space_handle_t, bus_size_t, uint8_t);
+void au_wired_w_2(void *, bus_space_handle_t, bus_size_t, uint16_t);
+void au_wired_w_4(void *, bus_space_handle_t, bus_size_t, uint32_t);
+void au_wired_w_8(void *, bus_space_handle_t, bus_size_t, uint64_t);
+void au_wired_wm_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *,
+    bus_size_t);
+void au_wired_wm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
+    bus_size_t);
+void au_wired_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
+    bus_size_t);
+void au_wired_wm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
+    bus_size_t);
+void au_wired_wr_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *,
+    bus_size_t);
+void au_wired_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
+    bus_size_t);
+void au_wired_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
+    bus_size_t);
+void au_wired_wr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
+    bus_size_t);
+void au_wired_sm_1(void *, bus_space_handle_t, bus_size_t, uint8_t,
+    bus_size_t);
+void au_wired_sm_2(void *, bus_space_handle_t, bus_size_t, uint16_t,
+    bus_size_t);
+void au_wired_sm_4(void *, bus_space_handle_t, bus_size_t, uint32_t,
+    bus_size_t);
+void au_wired_sm_8(void *, bus_space_handle_t, bus_size_t, uint64_t,
+    bus_size_t);
+void au_wired_sr_1(void *, bus_space_handle_t, bus_size_t, uint8_t,
+    bus_size_t);
+void au_wired_sr_2(void *, bus_space_handle_t, bus_size_t, uint16_t,
+    bus_size_t);
+void au_wired_sr_4(void *, bus_space_handle_t, bus_size_t, uint32_t,
+    bus_size_t);
+void au_wired_sr_8(void *, bus_space_handle_t, bus_size_t, uint64_t,
+    bus_size_t);
+void au_wired_c_1(void *, bus_space_handle_t, bus_size_t,
+    bus_space_handle_t, bus_size_t, bus_size_t);
+void au_wired_c_2(void *, bus_space_handle_t, bus_size_t,
+    bus_space_handle_t, bus_size_t, bus_size_t);
+void au_wired_c_4(void *, bus_space_handle_t, bus_size_t,
+    bus_space_handle_t, bus_size_t, bus_size_t);
+void au_wired_c_8(void *, bus_space_handle_t, bus_size_t,
+    bus_space_handle_t, bus_size_t, bus_size_t);
+uint16_t au_wired_rs_2(void *, bus_space_handle_t, bus_size_t);
+uint32_t au_wired_rs_4(void *, bus_space_handle_t, bus_size_t);
+uint64_t au_wired_rs_8(void *, bus_space_handle_t, bus_size_t);
+void au_wired_ws_2(void *, bus_space_handle_t, bus_size_t, uint16_t);
+void au_wired_ws_4(void *, bus_space_handle_t, bus_size_t, uint32_t);
+void au_wired_ws_8(void *, bus_space_handle_t, bus_size_t, uint64_t);
+void au_wired_rms_2(void *, bus_space_handle_t, bus_size_t, uint16_t *,
+    bus_size_t);
+void au_wired_rms_4(void *, bus_space_handle_t, bus_size_t, uint32_t *,
+    bus_size_t);
+void au_wired_rms_8(void *, bus_space_handle_t, bus_size_t, uint64_t *,
+    bus_size_t);
+void au_wired_rrs_2(void *, bus_space_handle_t, bus_size_t, uint16_t *,
+    bus_size_t);
+void au_wired_rrs_4(void *, bus_space_handle_t, bus_size_t, uint32_t *,
+    bus_size_t);
+void au_wired_rrs_8(void *, bus_space_handle_t, bus_size_t, uint64_t *,
+    bus_size_t);
+void au_wired_wms_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
+    bus_size_t);
+void au_wired_wms_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
+    bus_size_t);
+void au_wired_wms_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
+    bus_size_t);
+void au_wired_wrs_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *,
+    bus_size_t);
+void au_wired_wrs_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *,
+    bus_size_t);
+void au_wired_wrs_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *,
+    bus_size_t);
+
+int
+au_wired_map(void *cookie, bus_addr_t addr, bus_size_t size,
+    int flags, bus_space_handle_t *bshp, int acct)
+{
+       int                     err;
+       au_wired_cookie_t       *c = (au_wired_cookie_t *)cookie;
+       paddr_t                 pa;
+
+       /* make sure we can map this bus address */
+       if (addr < c->c_start ||
+           addr + size > c->c_start + c->c_size)
+               return EINVAL;
+
+       pa = c->c_pbase + (addr - c->c_start);
+
+       if (!mips3_wired_enter_region(addr, pa, size))
+               return ENOMEM;
+
+       /*
+        * bus addresses are taken from virtual address space.
+        */
+       if (acct && c->c_extent != NULL) {
+               err = extent_alloc_region(c->c_extent, addr, size, EX_NOWAIT);
+               if (err)
+                       return err;
+       }
+
+       *bshp = addr;
+
+       return 0;
+}
+
+void
+au_wired_unmap(void *cookie, bus_space_handle_t bsh, bus_size_t size, int acct)
+{
+       au_wired_cookie_t       *c = (au_wired_cookie_t *)cookie;
+
+       if (acct != 0 && c->c_extent != NULL) {
+               extent_free(c->c_extent, (vaddr_t)bsh, size, EX_NOWAIT);
+       }
+}
+
+int
+au_wired_subregion(void *cookie, bus_space_handle_t bsh,
+    bus_size_t offset, bus_size_t size, bus_space_handle_t *nbshp)
+{
+
+       *nbshp = bsh + offset;
+       return 0;
+}
+
+void *
+au_wired_vaddr(void *cookie, bus_space_handle_t bsh)
+{
+
+       return ((void *)bsh);
+}
+
+paddr_t
+au_wired_mmap(void *cookie, bus_addr_t addr, off_t off, int prot, int flags)
+{
+       au_wired_cookie_t       *c = (au_wired_cookie_t *)cookie;
+
+       /* I/O spaces should not be directly mmap'ed */
+       if (c->c_flags & AU_WIRED_SPACE_IO)
+               return -1;
+
+       if (addr < c->c_start || (addr + off) >= (c->c_start + c->c_size))
+               return -1;
+
+       return mips_btop(c->c_pbase + (addr - c->c_start) + off);
+}
+
+int
+au_wired_alloc(void *cookie, bus_addr_t start, bus_addr_t end,
+    bus_size_t size, bus_size_t align, bus_size_t boundary, int flags,
+    bus_addr_t *addrp, bus_space_handle_t *bshp)
+{
+       au_wired_cookie_t       *c = (au_wired_cookie_t *)cookie;
+       vaddr_t addr;
+       int err;
+       paddr_t pa;