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[src/trunk]: src/sys/dev/pci Add support for the NVIDIA nForce ATA100 and nFo...
details: https://anonhg.NetBSD.org/src/rev/018adccfa691
branches: trunk
changeset: 542242:018adccfa691
user: thorpej <thorpej%NetBSD.org@localhost>
date: Fri Jan 24 04:53:13 2003 +0000
description:
Add support for the NVIDIA nForce ATA100 and nForce2 ATA133
IDE controllers, which are more-or-less compatible with the
AMD controllers.
XXX Need to determine the correct timing value for the nForce2
XXX at Ultra133, so we cap it at Ultra100, for now.
diffstat:
sys/dev/pci/pciide.c | 69 +++++++++++++++++++++++++++++++++++--------
sys/dev/pci/pciide_amd_reg.h | 14 ++++++--
sys/dev/pci/pciidevar.h | 7 +++-
3 files changed, 71 insertions(+), 19 deletions(-)
diffs (203 lines):
diff -r 1c092febfc2a -r 018adccfa691 sys/dev/pci/pciide.c
--- a/sys/dev/pci/pciide.c Fri Jan 24 03:16:08 2003 +0000
+++ b/sys/dev/pci/pciide.c Fri Jan 24 04:53:13 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pciide.c,v 1.176 2002/12/26 20:54:03 matt Exp $ */
+/* $NetBSD: pciide.c,v 1.177 2003/01/24 04:53:13 thorpej Exp $ */
/*
@@ -76,7 +76,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.176 2002/12/26 20:54:03 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.177 2003/01/24 04:53:13 thorpej Exp $");
#ifndef WDCDEBUG
#define WDCDEBUG
@@ -341,6 +341,24 @@
}
};
+const struct pciide_product_desc pciide_nvidia_products[] = {
+ { PCI_PRODUCT_NVIDIA_NFORCE_ATA100,
+ 0,
+ "NVIDIA nForce IDE Controller",
+ amd7x6_chip_map
+ },
+ { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133,
+ 0,
+ "NVIDIA nForce2 IDE Controller",
+ amd7x6_chip_map
+ },
+ { 0,
+ 0,
+ NULL,
+ NULL
+ }
+};
+
const struct pciide_product_desc pciide_cmd_products[] = {
{ PCI_PRODUCT_CMDTECH_640,
0,
@@ -624,6 +642,7 @@
{ PCI_VENDOR_SERVERWORKS, pciide_serverworks_products },
{ PCI_VENDOR_SYMPHONY, pciide_symphony_products },
{ PCI_VENDOR_WINBOND, pciide_winbond_products },
+ { PCI_VENDOR_NVIDIA, pciide_nvidia_products },
{ 0, NULL }
};
@@ -723,6 +742,7 @@
char devinfo[256];
const char *displaydev;
+ sc->sc_pci_vendor = PCI_VENDOR(pa->pa_id);
sc->sc_pp = pciide_lookup_product(pa->pa_id);
if (sc->sc_pp == NULL) {
sc->sc_pp = &default_product_desc;
@@ -2016,19 +2036,40 @@
sc->sc_wdcdev.PIO_cap = 4;
sc->sc_wdcdev.DMA_cap = 2;
- switch (sc->sc_pp->ide_product) {
- case PCI_PRODUCT_AMD_PBC766_IDE:
- case PCI_PRODUCT_AMD_PBC768_IDE:
- case PCI_PRODUCT_AMD_PBC8111_IDE:
- sc->sc_wdcdev.UDMA_cap = 5;
+ switch (sc->sc_pci_vendor) {
+ case PCI_VENDOR_AMD:
+ switch (sc->sc_pp->ide_product) {
+ case PCI_PRODUCT_AMD_PBC766_IDE:
+ case PCI_PRODUCT_AMD_PBC768_IDE:
+ case PCI_PRODUCT_AMD_PBC8111_IDE:
+ sc->sc_wdcdev.UDMA_cap = 5;
+ break;
+ default:
+ sc->sc_wdcdev.UDMA_cap = 4;
+ }
+ sc->sc_amd_regbase = AMD7X6_AMD_REGBASE;
break;
+
+ case PCI_VENDOR_NVIDIA:
+ switch (sc->sc_pp->ide_product) {
+ case PCI_PRODUCT_NVIDIA_NFORCE_ATA100:
+ sc->sc_wdcdev.UDMA_cap = 5;
+ break;
+ case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133:
+ sc->sc_wdcdev.UDMA_cap = 5; /* XXX */
+ break;
+ }
+ sc->sc_amd_regbase = AMD7X6_NVIDIA_REGBASE;
+ break;
+
default:
- sc->sc_wdcdev.UDMA_cap = 4;
+ panic("amd7x6_chip_map: unknown vendor");
}
sc->sc_wdcdev.set_modes = amd7x6_setup_channel;
sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
- chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN);
+ chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag,
+ AMD7X6_CHANSTATUS_EN(sc));
WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable),
DEBUG_PROBE);
@@ -2053,7 +2094,7 @@
amd7x6_setup_channel(&cp->wdc_channel);
}
- pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN,
+ pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN(sc),
chanenable);
return;
}
@@ -2074,8 +2115,8 @@
#endif
idedma_ctl = 0;
- datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM);
- udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA);
+ datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc));
+ udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc));
datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel);
udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel);
@@ -2155,8 +2196,8 @@
idedma_ctl);
}
pciide_print_modes(cp);
- pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg);
- pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg);
+ pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc), datatim_reg);
+ pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc), udmatim_reg);
}
void
diff -r 1c092febfc2a -r 018adccfa691 sys/dev/pci/pciide_amd_reg.h
--- a/sys/dev/pci/pciide_amd_reg.h Fri Jan 24 03:16:08 2003 +0000
+++ b/sys/dev/pci/pciide_amd_reg.h Fri Jan 24 04:53:13 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pciide_amd_reg.h,v 1.4 2001/10/21 18:49:20 thorpej Exp $ */
+/* $NetBSD: pciide_amd_reg.h,v 1.5 2003/01/24 04:53:14 thorpej Exp $ */
/*
* Copyright (c) 2000 David Sainty.
@@ -54,13 +54,19 @@
*/
#define AMD756_CHIPREV_DISABLEDMA(rev) ((rev) <= AMD756_CHIPREV_D2)
+/*
+ * The nVidia nForce and nForce2 IDE controllers are compatible with
+ * the AMD controllers, but their registers are offset 0x10 bytes.
+ */
+#define AMD7X6_AMD_REGBASE 0x40
+#define AMD7X6_NVIDIA_REGBASE 0x50
/* Channel enable */
-#define AMD7X6_CHANSTATUS_EN 0x40
+#define AMD7X6_CHANSTATUS_EN(sc) ((sc)->sc_amd_regbase + 0x00)
#define AMD7X6_CHAN_EN(chan) (0x01 << (1 - (chan)))
/* Data port timing controls */
-#define AMD7X6_DATATIM 0x48
+#define AMD7X6_DATATIM(sc) ((sc)->sc_amd_regbase + 0x08)
#define AMD7X6_DATATIM_MASK(channel) (0xffff << ((1 - (channel)) << 4))
#define AMD7X6_DATATIM_RECOV(channel, drive, x) (((x) & 0xf) << \
(((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
@@ -71,7 +77,7 @@
static const int8_t amd7x6_pio_rec[] = {0x08, 0x08, 0x08, 0x02, 0x00};
/* Ultra-DMA/33 control */
-#define AMD7X6_UDMA 0x50
+#define AMD7X6_UDMA(sc) ((sc)->sc_amd_regbase + 0x10)
#define AMD7X6_UDMA_MASK(channel) (0xffff << ((1 - (channel)) << 4))
#define AMD7X6_UDMA_TIME(channel, drive, x) (((x) & 0x7) << \
(((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
diff -r 1c092febfc2a -r 018adccfa691 sys/dev/pci/pciidevar.h
--- a/sys/dev/pci/pciidevar.h Fri Jan 24 03:16:08 2003 +0000
+++ b/sys/dev/pci/pciidevar.h Fri Jan 24 04:53:13 2003 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: pciidevar.h,v 1.7 2001/06/08 04:48:58 simonb Exp $ */
+/* $NetBSD: pciidevar.h,v 1.8 2003/01/24 04:53:14 thorpej Exp $ */
/*
* Copyright (c) 1998 Christopher G. Demetriou. All rights reserved.
@@ -52,10 +52,15 @@
bus_space_handle_t sc_dma_ioh;
bus_dma_tag_t sc_dmat;
+ /* For AMD/nVidia */
+ bus_addr_t sc_amd_regbase;
+
/* For Cypress */
const struct cy82c693_handle *sc_cy_handle;
int sc_cy_compatchan;
+ /* Vendor info (for interpreting Chip description) */
+ uint32_t sc_pci_vendor;
/* Chip description */
const struct pciide_product_desc *sc_pp;
/* common definitions */
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