[src/trunk]: src/sys/arch/arm/arm Use the RET macro, rather than "bx lr" unco...

[thorpej <thorpej%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/24c455d9fc7a
branches:  trunk
changeset: 569556:24c455d9fc7a
user:      thorpej <thorpej%NetBSD.org@localhost>
date:      Mon Aug 23 20:53:56 2004 +0000

description:
Use the RET macro, rather than "bx lr" unconditionally.  Makes this file
compile again for the INTEGRATOR configuration.

diffstat:

 sys/arch/arm/arm/cpufunc_asm_arm10.S |  24 ++++++++++++------------
 1 files changed, 12 insertions(+), 12 deletions(-)

diffs (104 lines):

diff -r 9c548e72e5b0 -r 24c455d9fc7a sys/arch/arm/arm/cpufunc_asm_arm10.S
--- a/sys/arch/arm/arm/cpufunc_asm_arm10.S      Mon Aug 23 20:49:28 2004 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_arm10.S      Mon Aug 23 20:53:56 2004 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: cpufunc_asm_arm10.S,v 1.1 2003/09/06 09:12:29 rearnsha Exp $   */
+/*     $NetBSD: cpufunc_asm_arm10.S,v 1.2 2004/08/23 20:53:56 thorpej Exp $    */
 
 /*
  * Copyright (c) 2002 ARM Limited
@@ -48,7 +48,7 @@
        mcr     p15, 0, r0, c2, c0, 0   /* load new TTB */
 
        mcr     p15, 0, r0, c8, c7, 0   /* invalidate I+D TLBs */
-       bx      lr
+       RET
 
 /*
  * TLB functions
@@ -56,11 +56,11 @@
 ENTRY(arm10_tlb_flushID_SE)
        mcr     p15, 0, r0, c8, c6, 1   /* flush D tlb single entry */
        mcr     p15, 0, r0, c8, c5, 1   /* flush I tlb single entry */
-       bx      lr
+       RET
 
 ENTRY(arm10_tlb_flushI_SE)
        mcr     p15, 0, r0, c8, c5, 1   /* flush I tlb single entry */
-       bx      lr
+       RET
        
 
 /*
@@ -88,7 +88,7 @@
        subs    r1, r1, ip
        bpl     .Larm10_sync_next
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
-       bx      lr
+       RET
 
 ENTRY_NP(arm10_icache_sync_all)
 .Larm10_icache_sync_all:
@@ -114,7 +114,7 @@
        subs    s_max, s_max, s_inc
        bpl     .Lnext_set              /* Next set */
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
-       bx      lr
+       RET
 
 .Larm10_line_size:
        .word   _C_LABEL(arm_pdcache_line_size)
@@ -134,7 +134,7 @@
        subs    r1, r1, ip
        bpl     .Larm10_wb_next
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
-       bx      lr
+       RET
        
 ENTRY(arm10_dcache_wbinv_range)
        ldr     ip, .Larm10_line_size
@@ -151,7 +151,7 @@
        subs    r1, r1, ip
        bpl     .Larm10_wbinv_next
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
-       bx      lr
+       RET
        
 /*
  * Note, we must not invalidate everything.  If the range is too big we
@@ -172,7 +172,7 @@
        subs    r1, r1, ip
        bpl     .Larm10_inv_next
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
-       bx      lr
+       RET
 
 ENTRY(arm10_idcache_wbinv_range)
        ldr     ip, .Larm10_line_size
@@ -190,7 +190,7 @@
        subs    r1, r1, ip
        bpl     .Larm10_id_wbinv_next
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
-       bx      lr
+       RET
 
 ENTRY_NP(arm10_idcache_wbinv_all)
 .Larm10_idcache_wbinv_all:
@@ -217,7 +217,7 @@
        subs    s_max, s_max, s_inc
        bpl     .Lnext_set_inv          /* Next set */
        mcr     p15, 0, r0, c7, c10, 4  /* drain the write buffer */
-       bx      lr
+       RET
 
 .Larm10_cache_data:
        .word   _C_LABEL(arm10_dcache_sets_max)
@@ -244,7 +244,7 @@
        nop
        nop
        nop
-       bx      lr
+       RET
 
        .bss