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[src/trunk]: src/sys/arch au_icu.c is in mips/ and should not depend on evbmi...
details: https://anonhg.NetBSD.org/src/rev/e00dc3e26a63
branches: trunk
changeset: 588144:e00dc3e26a63
user: gdamore <gdamore%NetBSD.org@localhost>
date: Thu Feb 09 18:03:12 2006 +0000
description:
au_icu.c is in mips/ and should not depend on evbmips intr handler struct.
convert various u_int32_t to preferred uint32_t.
diffstat:
sys/arch/evbmips/alchemy/mach_intr.c | 7 +++----
sys/arch/evbmips/include/intr.h | 8 ++++----
sys/arch/evbmips/malta/malta_intr.c | 10 +++++-----
sys/arch/mips/alchemy/au_icu.c | 29 ++++++++++++++++++-----------
4 files changed, 30 insertions(+), 24 deletions(-)
diffs (196 lines):
diff -r 18d8c1d7fc58 -r e00dc3e26a63 sys/arch/evbmips/alchemy/mach_intr.c
--- a/sys/arch/evbmips/alchemy/mach_intr.c Thu Feb 09 16:40:49 2006 +0000
+++ b/sys/arch/evbmips/alchemy/mach_intr.c Thu Feb 09 18:03:12 2006 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: mach_intr.c,v 1.1 2006/02/07 18:57:12 gdamore Exp $ */
+/* $NetBSD: mach_intr.c,v 1.2 2006/02/09 18:03:12 gdamore Exp $ */
/*-
* Copyright (c) 2001 The NetBSD Foundation, Inc.
@@ -45,7 +45,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mach_intr.c,v 1.1 2006/02/07 18:57:12 gdamore Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mach_intr.c,v 1.2 2006/02/09 18:03:12 gdamore Exp $");
#include "opt_ddb.h"
@@ -70,8 +70,7 @@
}
void
-evbmips_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc,
- u_int32_t ipending)
+evbmips_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
{
au_iointr(status, cause, pc, ipending);
diff -r 18d8c1d7fc58 -r e00dc3e26a63 sys/arch/evbmips/include/intr.h
--- a/sys/arch/evbmips/include/intr.h Thu Feb 09 16:40:49 2006 +0000
+++ b/sys/arch/evbmips/include/intr.h Thu Feb 09 18:03:12 2006 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: intr.h,v 1.6 2005/11/27 14:01:45 yamt Exp $ */
+/* $NetBSD: intr.h,v 1.7 2006/02/09 18:03:12 gdamore Exp $ */
/*-
* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
@@ -88,8 +88,8 @@
#ifdef _KERNEL
-extern const u_int32_t ipl_sr_bits[_IPL_N];
-extern const u_int32_t ipl_si_to_sr[_IPL_NSOFT];
+extern const uint32_t ipl_sr_bits[_IPL_N];
+extern const uint32_t ipl_si_to_sr[_IPL_NSOFT];
extern int _splraise(int);
extern int _spllower(int);
@@ -121,7 +121,7 @@
void evbmips_intr_init(void);
void intr_init(void);
-void evbmips_iointr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
+void evbmips_iointr(uint32_t, uint32_t, uint32_t, uint32_t);
void *evbmips_intr_establish(int, int (*)(void *), void *);
void evbmips_intr_disestablish(void *);
#endif /* _KERNEL */
diff -r 18d8c1d7fc58 -r e00dc3e26a63 sys/arch/evbmips/malta/malta_intr.c
--- a/sys/arch/evbmips/malta/malta_intr.c Thu Feb 09 16:40:49 2006 +0000
+++ b/sys/arch/evbmips/malta/malta_intr.c Thu Feb 09 18:03:12 2006 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: malta_intr.c,v 1.10 2005/11/25 13:55:14 simonb Exp $ */
+/* $NetBSD: malta_intr.c,v 1.11 2006/02/09 18:03:12 gdamore Exp $ */
/*
* Copyright 2001, 2002 Wasabi Systems, Inc.
@@ -40,7 +40,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.10 2005/11/25 13:55:14 simonb Exp $");
+__KERNEL_RCSID(0, "$NetBSD: malta_intr.c,v 1.11 2006/02/09 18:03:12 gdamore Exp $");
#include <sys/param.h>
#include <sys/device.h>
@@ -64,7 +64,7 @@
* This is a mask of bits to clear in the SR when we go to a
* given hardware interrupt priority level.
*/
-const u_int32_t ipl_sr_bits[_IPL_N] = {
+const uint32_t ipl_sr_bits[_IPL_N] = {
0, /* 0: IPL_NONE */
MIPS_SOFT_INT_MASK_0, /* 1: IPL_SOFT */
@@ -104,7 +104,7 @@
* given software interrupt priority level.
* Hardware ipls are port/board specific.
*/
-const u_int32_t mips_ipl_si_to_sr[_IPL_NSOFT] = {
+const uint32_t mips_ipl_si_to_sr[_IPL_NSOFT] = {
MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
MIPS_SOFT_INT_MASK_1, /* IPL_SOFTNET */
@@ -165,7 +165,7 @@
malta_cal_timer(bus_space_tag_t st, bus_space_handle_t sh)
{
uint32_t ctrdiff[4], startctr, endctr;
- u_int8_t regc;
+ uint8_t regc;
int i;
/* Disable interrupts first. */
diff -r 18d8c1d7fc58 -r e00dc3e26a63 sys/arch/mips/alchemy/au_icu.c
--- a/sys/arch/mips/alchemy/au_icu.c Thu Feb 09 16:40:49 2006 +0000
+++ b/sys/arch/mips/alchemy/au_icu.c Thu Feb 09 18:03:12 2006 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: au_icu.c,v 1.13 2006/02/06 23:23:53 gdamore Exp $ */
+/* $NetBSD: au_icu.c,v 1.14 2006/02/09 18:03:12 gdamore Exp $ */
/*-
* Copyright (c) 2006 Itronix Inc.
@@ -75,7 +75,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.13 2006/02/06 23:23:53 gdamore Exp $");
+__KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.14 2006/02/09 18:03:12 gdamore Exp $");
#include "opt_ddb.h"
@@ -93,14 +93,14 @@
#include <mips/alchemy/include/aureg.h>
#include <mips/alchemy/include/auvar.h>
-#define REGVAL(x) *((volatile u_int32_t *)(MIPS_PHYS_TO_KSEG1((x))))
+#define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x))))
/*
* This is a mask of bits to clear in the SR when we go to a
* given hardware interrupt priority level.
*/
-const u_int32_t ipl_sr_bits[_IPL_N] = {
+const uint32_t ipl_sr_bits[_IPL_N] = {
0, /* 0: IPL_NONE */
MIPS_SOFT_INT_MASK_0, /* 1: IPL_SOFT */
@@ -138,7 +138,7 @@
* given software interrupt priority level.
* Hardware ipls are port/board specific.
*/
-const u_int32_t mips_ipl_si_to_sr[_IPL_NSOFT] = {
+const uint32_t mips_ipl_si_to_sr[_IPL_NSOFT] = {
MIPS_SOFT_INT_MASK_0, /* IPL_SOFT */
MIPS_SOFT_INT_MASK_0, /* IPL_SOFTCLOCK */
MIPS_SOFT_INT_MASK_0, /* IPL_SOFTNET */
@@ -155,8 +155,15 @@
#define NINTRS 4 /* MIPS INT0 - INT3 */
+struct au_intrhand {
+ LIST_ENTRY(au_intrhand) ih_q;
+ int (*ih_func)(void *);
+ void *ih_arg;
+ int ih_irq;
+};
+
struct au_cpuintr {
- LIST_HEAD(, evbmips_intrhand) cintr_list;
+ LIST_HEAD(, au_intrhand) cintr_list;
struct evcnt cintr_count;
};
@@ -199,7 +206,7 @@
au_intr_establish(int irq, int req, int level, int type,
int (*func)(void *), void *arg)
{
- struct evbmips_intrhand *ih;
+ struct au_intrhand *ih;
uint32_t icu_base;
int cpu_int, s;
struct au_chipdep *chip;
@@ -282,7 +289,7 @@
void
au_intr_disestablish(void *cookie)
{
- struct evbmips_intrhand *ih = cookie;
+ struct au_intrhand *ih = cookie;
uint32_t icu_base;
int irq, s;
@@ -318,11 +325,11 @@
}
void
-au_iointr(u_int32_t status, u_int32_t cause, u_int32_t pc, u_int32_t ipending)
+au_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending)
{
- struct evbmips_intrhand *ih;
+ struct au_intrhand *ih;
int level;
- u_int32_t icu_base = 0, irqmask = 0; /* Both XXX gcc */
+ uint32_t icu_base = 0, irqmask = 0; /* Both XXX gcc */
for (level = 3; level >= 0; level--) {
if ((ipending & (MIPS_INT_MASK_0 << level)) == 0)
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