[src/trunk]: src/sys/arch/mips/alchemy Fix error calling interrupt too many t...

[gdamore <gdamore%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/b62f936fd8e1
branches:  trunk
changeset: 588160:b62f936fd8e1
user:      gdamore <gdamore%NetBSD.org@localhost>
date:      Fri Feb 10 00:56:41 2006 +0000

description:
Fix error calling interrupt too many times (found with vmstat -e).
Replace "&&" with "&" when doing bit mask operations.  Doh!

diffstat:

 sys/arch/mips/alchemy/au_icu.c |  12 +++++++-----
 1 files changed, 7 insertions(+), 5 deletions(-)

diffs (36 lines):

diff -r d4fd2cb178f3 -r b62f936fd8e1 sys/arch/mips/alchemy/au_icu.c
--- a/sys/arch/mips/alchemy/au_icu.c    Fri Feb 10 00:53:04 2006 +0000
+++ b/sys/arch/mips/alchemy/au_icu.c    Fri Feb 10 00:56:41 2006 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: au_icu.c,v 1.15 2006/02/10 00:22:42 gdamore Exp $      */
+/*     $NetBSD: au_icu.c,v 1.16 2006/02/10 00:56:41 gdamore Exp $      */
 
 /*-
  * Copyright (c) 2006 Itronix Inc.
@@ -75,7 +75,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.15 2006/02/10 00:22:42 gdamore Exp $");
+__KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.16 2006/02/10 00:56:41 gdamore Exp $");
 
 #include "opt_ddb.h"
 
@@ -373,12 +373,14 @@
                LIST_FOREACH(ih, &au_cpuintrs[level].cintr_list, ih_q) {
                        int irq = (1 << ih->ih_irq);
 
-                       if ((irq && irqmask) && (irq && irqstat)) {
+                       if ((irq & irqmask) && (irq & irqstat)) {
                                au_icu_intrtab[ih->ih_irq].intr_count.ev_count++;
                                (*ih->ih_func)(ih->ih_arg);
 
-                               REGVAL(icu_base + IC_MASK_CLEAR) = irq;
-                               REGVAL(icu_base + IC_MASK_SET) = irq;
+                               if (REGVAL(icu_base + IC_MASK_READ) & irq) {
+                                       REGVAL(icu_base + IC_MASK_CLEAR) = irq;
+                                       REGVAL(icu_base + IC_MASK_SET) = irq;
+                               }
                        }
                }
                cause &= ~(MIPS_INT_MASK_0 << level);