[src/trunk]: src/sys/arch/aarch64 Fetch ID_AA64MMFR2_EL1. Okayed by Nick the ...

[maxv <maxv%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/8ea2e16027ff
branches:  trunk
changeset: 744272:8ea2e16027ff
user:      maxv <maxv%NetBSD.org@localhost>
date:      Tue Jan 28 17:47:50 2020 +0000

description:
Fetch ID_AA64MMFR2_EL1. Okayed by Nick the other day.

diffstat:

 sys/arch/aarch64/aarch64/cpu.c    |   7 +++----
 sys/arch/aarch64/include/armreg.h |  19 +++++++++++++------
 2 files changed, 16 insertions(+), 10 deletions(-)

diffs (80 lines):

diff -r 8514e82f4179 -r 8ea2e16027ff sys/arch/aarch64/aarch64/cpu.c
--- a/sys/arch/aarch64/aarch64/cpu.c    Tue Jan 28 17:36:42 2020 +0000
+++ b/sys/arch/aarch64/aarch64/cpu.c    Tue Jan 28 17:47:50 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.38 2020/01/27 16:25:08 skrll Exp $ */
+/* $NetBSD: cpu.c,v 1.39 2020/01/28 17:47:50 maxv Exp $ */
 
 /*
  * Copyright (c) 2017 Ryo Shimizu <ryo%nerv.org@localhost>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.38 2020/01/27 16:25:08 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: cpu.c,v 1.39 2020/01/28 17:47:50 maxv Exp $");
 
 #include "locators.h"
 #include "opt_arm_debug.h"
@@ -460,8 +460,7 @@
 
        id->ac_aa64mmfr0 = reg_id_aa64mmfr0_el1_read();
        id->ac_aa64mmfr1 = reg_id_aa64mmfr1_el1_read();
-       /* Only in ARMv8.2. */
-       id->ac_aa64mmfr2 = 0 /* reg_id_aa64mmfr2_el1_read() */;
+       id->ac_aa64mmfr2 = reg_id_aa64mmfr2_el1_read();
 
        id->ac_mvfr0     = reg_mvfr0_el1_read();
        id->ac_mvfr1     = reg_mvfr1_el1_read();
diff -r 8514e82f4179 -r 8ea2e16027ff sys/arch/aarch64/include/armreg.h
--- a/sys/arch/aarch64/include/armreg.h Tue Jan 28 17:36:42 2020 +0000
+++ b/sys/arch/aarch64/include/armreg.h Tue Jan 28 17:47:50 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.32 2020/01/28 17:33:07 maxv Exp $ */
+/* $NetBSD: armreg.h,v 1.33 2020/01/28 17:47:51 maxv Exp $ */
 
 /*-
  * Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -35,8 +35,8 @@
 #include <arm/cputypes.h>
 #include <sys/types.h>
 
-#define AARCH64REG_READ_INLINE2(regname, regdesc)              \
-static __inline uint64_t                                       \
+#define AARCH64REG_READ_INLINE3(regname, regdesc, fnattrs)     \
+static __inline uint64_t fnattrs                               \
 reg_##regname##_read(void)                                     \
 {                                                              \
        uint64_t __rv;                                          \
@@ -44,13 +44,19 @@
        return __rv;                                            \
 }
 
-#define AARCH64REG_WRITE_INLINE2(regname, regdesc)             \
-static __inline void                                           \
+#define AARCH64REG_READ_INLINE2(regname, regdesc)              \
+       AARCH64REG_READ_INLINE3(regname, regdesc, )
+
+#define AARCH64REG_WRITE_INLINE3(regname, regdesc, fnattrs)    \
+static __inline void fnattrs                                   \
 reg_##regname##_write(uint64_t __val)                          \
 {                                                              \
        __asm __volatile("msr " #regdesc ", %0" :: "r"(__val)); \
 }
 
+#define AARCH64REG_WRITE_INLINE2(regname, regdesc)             \
+       AARCH64REG_WRITE_INLINE3(regname, regdesc, )
+
 #define AARCH64REG_WRITEIMM_INLINE2(regname, regdesc)          \
 static __inline void                                           \
 reg_##regname##_write(uint64_t __val)                          \
@@ -329,7 +335,8 @@
 #define         ID_AA64MMFR1_EL1_HAFDBS_A       1
 #define         ID_AA64MMFR1_EL1_HAFDBS_AD      2
 
-AARCH64REG_READ_INLINE(id_aa64mmfr2_el1)
+AARCH64REG_READ_INLINE3(id_aa64mmfr2_el1, id_aa64mmfr2_el1,
+    __attribute__((target("arch=armv8.2-a"))))
 
 #define        ID_AA64MMFR2_EL1_E0PD           __BITS(63,60)
 #define         ID_AA64MMFR2_EL1_E0PD_NONE      0