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[src/netbsd-9]: src/sys/arch/powerpc/ibm4xx Pull up following revision(s) (re...
details: https://anonhg.NetBSD.org/src/rev/f2062a8407df
branches: netbsd-9
changeset: 745295:f2062a8407df
user: martin <martin%NetBSD.org@localhost>
date: Thu Feb 27 18:43:41 2020 +0000
description:
Pull up following revision(s) (requested by rin in ticket #735):
sys/arch/powerpc/ibm4xx/trap.c: revision 1.71
sys/arch/powerpc/ibm4xx/trap.c: revision 1.72
sys/arch/powerpc/ibm4xx/trap.c: revision 1.73
sys/arch/powerpc/ibm4xx/trap.c: revision 1.74
sys/arch/powerpc/ibm4xx/trap.c: revision 1.75
sys/arch/powerpc/ibm4xx/trap.c: revision 1.76
sys/arch/powerpc/ibm4xx/trap.c: revision 1.77
sys/arch/powerpc/ibm4xx/trap.c: revision 1.78
Sort headers.
-
Sort more headers...
-
Convert mi_userret(9) into powerpc-specific userret().
This is necessary in order to support RAS.
There are some sanity checks in userret() as well.
-
Oops, sort header again. My bad...
-
Comment out badaddr() and badaddr_read() on ibm4xx for now.
They are not used nor exposed externally in any header file; these
functions may have never been tested so far.
Enable them again when necessary.
Note that badaddr() for oea is used by macppc port, where it is
declared as an external function.
-
Cosmetic changes for assembler codes. No binary changes.
-
Tiny improvements to copyin() and copyout():
- Use lwz/stw instead of 4-byte lswi/stswi for 405 and later, which
support unaligned word load/store by hardware. In many cases, both
source and destination are aligned on word boundaries.
- Use dcbst instead of dcbf to flush cache. The former does not
invalidate the cache line. Copied data should be used soon after.
-
Do not try to recovery from data page fault in interrupt context;
catch up belatedly with powerpc/trap.c rev 1.49 and etc.:
http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/powerpc/powerpc/trap.c#rev1.49
diffstat:
sys/arch/powerpc/ibm4xx/trap.c | 143 ++++++++++++++++++++++++----------------
1 files changed, 87 insertions(+), 56 deletions(-)
diffs (271 lines):
diff -r 42fc50594f6f -r f2062a8407df sys/arch/powerpc/ibm4xx/trap.c
--- a/sys/arch/powerpc/ibm4xx/trap.c Thu Feb 27 18:34:12 2020 +0000
+++ b/sys/arch/powerpc/ibm4xx/trap.c Thu Feb 27 18:43:41 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: trap.c,v 1.70 2019/04/07 05:25:55 thorpej Exp $ */
+/* $NetBSD: trap.c,v 1.70.4.1 2020/02/27 18:43:41 martin Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@@ -67,7 +67,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.70 2019/04/07 05:25:55 thorpej Exp $");
+__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.70.4.1 2020/02/27 18:43:41 martin Exp $");
#include "opt_altivec.h"
#include "opt_ddb.h"
@@ -76,13 +76,12 @@
#define __UFETCHSTORE_PRIVATE
#include <sys/param.h>
+#include <sys/cpu.h>
+#include <sys/kauth.h>
#include <sys/proc.h>
#include <sys/reboot.h>
#include <sys/syscall.h>
#include <sys/systm.h>
-#include <sys/userret.h>
-#include <sys/kauth.h>
-#include <sys/cpu.h>
#if defined(KGDB)
#include <sys/kgdb.h>
@@ -100,10 +99,11 @@
#include <powerpc/db_machdep.h>
#include <powerpc/spr.h>
-#include <powerpc/ibm4xx/spr.h>
+#include <powerpc/userret.h>
#include <powerpc/ibm4xx/cpu.h>
#include <powerpc/ibm4xx/pmap.h>
+#include <powerpc/ibm4xx/spr.h>
#include <powerpc/ibm4xx/tlb.h>
#include <powerpc/fpu/fpu_extern.h>
@@ -116,9 +116,11 @@
static int fix_unaligned(struct lwp *l, struct trapframe *tf);
void trap(struct trapframe *); /* Called from locore / trap_subr */
-/* Why are these not defined in a header? */
+#if 0
+/* Not currently used nor exposed externally in any header file */
int badaddr(void *, size_t);
int badaddr_read(void *, size_t, int *);
+#endif
int ctx_setup(int, int);
#ifdef DEBUG
@@ -180,7 +182,15 @@
{
struct vm_map *map;
vaddr_t va;
- struct faultbuf *fb = NULL;
+ struct faultbuf *fb;
+
+ pcb = lwp_getpcb(l);
+ fb = pcb->pcb_onfault;
+
+ if (curcpu()->ci_idepth >= 0) {
+ rv = EFAULT;
+ goto out;
+ }
va = tf->tf_dear;
if (tf->tf_pid == KERNEL_PID) {
@@ -198,13 +208,12 @@
(ftype & VM_PROT_WRITE) ? "write" : "read",
(void *)va, tf->tf_esr));
- pcb = lwp_getpcb(l);
- fb = pcb->pcb_onfault;
pcb->pcb_onfault = NULL;
rv = uvm_fault(map, trunc_page(va), ftype);
pcb->pcb_onfault = fb;
if (rv == 0)
return;
+out:
if (fb != NULL) {
tf->tf_pid = KERNEL_PID;
tf->tf_srr0 = fb->fb_pc;
@@ -348,8 +357,8 @@
panic("trap");
}
- /* Invoke MI userret code */
- mi_userret(l);
+ /* Invoke powerpc userret code */
+ userret(l, tf);
}
int
@@ -416,43 +425,53 @@
}
__asm volatile(
- " mfmsr %[msr];" /* Save MSR */
- " li %[pid],0x20; "
- " andc %[pid],%[msr],%[pid]; mtmsr %[pid];" /* Disable IMMU */
- " mfpid %[pid];" /* Save old PID */
+ " mfmsr %[msr];" /* Save MSR */
+ " li %[pid],0x20;"
+ " andc %[pid],%[msr],%[pid]; mtmsr %[pid];" /* Disable IMMU */
+ " mfpid %[pid];" /* Save old PID */
" sync; isync;"
- " srwi. %[count],%[len],0x2;" /* How many words? */
- " beq- 2f;" /* No words. Go do bytes */
+ " srwi. %[count],%[len],0x2;" /* How many words? */
+ " beq- 2f;" /* No words. Go do bytes */
" mtctr %[count];"
"1: mtpid %[ctx]; sync;"
- " lswi %[tmp],%[udaddr],4;" /* Load user word */
- " addi %[udaddr],%[udaddr],0x4;" /* next udaddr word */
+#ifdef PPC_IBM403
+ " lswi %[tmp],%[udaddr],4;" /* Load user word */
+#else
+ " lwz %[tmp],0(%[udaddr]);"
+#endif
+ " addi %[udaddr],%[udaddr],0x4;" /* next udaddr word */
" sync; isync;"
- " mtpid %[pid];sync;"
- " stswi %[tmp],%[kaddr],4;" /* Store kernel word */
- " dcbf 0,%[kaddr];" /* flush cache */
- " addi %[kaddr],%[kaddr],0x4;" /* next udaddr word */
+ " mtpid %[pid]; sync;"
+#ifdef PPC_IBM403
+ " stswi %[tmp],%[kaddr],4;" /* Store kernel word */
+#else
+ " stw %[tmp],0(%[kaddr]);"
+#endif
+ " dcbst 0,%[kaddr];" /* flush cache */
+ " addi %[kaddr],%[kaddr],0x4;" /* next udaddr word */
" sync; isync;"
- " bdnz 1b;" /* repeat */
+ " bdnz 1b;" /* repeat */
- "2: andi. %[count],%[len],0x3;" /* How many remaining bytes? */
+ "2: andi. %[count],%[len],0x3;" /* How many remaining bytes? */
" addi %[count],%[count],0x1;"
" mtctr %[count];"
- "3: bdz 10f;" /* while count */
- " mtpid %[ctx];sync;"
- " lbz %[tmp],0(%[udaddr]);" /* Load user byte */
- " addi %[udaddr],%[udaddr],0x1;" /* next udaddr byte */
+ "3: bdz 10f;" /* while count */
+ " mtpid %[ctx]; sync;"
+ " lbz %[tmp],0(%[udaddr]);" /* Load user byte */
+ " addi %[udaddr],%[udaddr],0x1;" /* next udaddr byte */
" sync; isync;"
" mtpid %[pid]; sync;"
- " stb %[tmp],0(%[kaddr]);" /* Store kernel byte */
- " dcbf 0,%[kaddr];" /* flush cache */
+ " stb %[tmp],0(%[kaddr]);" /* Store kernel byte */
+ " dcbst 0,%[kaddr];" /* flush cache */
" addi %[kaddr],%[kaddr],0x1;"
" sync; isync;"
" b 3b;"
- "10:mtpid %[pid]; mtmsr %[msr]; sync; isync;" /* Restore PID and MSR */
+ "10:mtpid %[pid]; mtmsr %[msr]; sync; isync;"
+ /* Restore PID and MSR */
: [msr] "=&r" (msr), [pid] "=&r" (pid), [tmp] "=&r" (tmp)
- : [udaddr] "b" (udaddr), [ctx] "b" (ctx), [kaddr] "b" (kaddr), [len] "b" (len), [count] "b" (count));
+ : [udaddr] "b" (udaddr), [ctx] "b" (ctx), [kaddr] "b" (kaddr),
+ [len] "b" (len), [count] "b" (count));
curpcb->pcb_onfault = NULL;
return 0;
@@ -513,43 +532,53 @@
}
__asm volatile(
- " mfmsr %[msr];" /* Save MSR */ \
- " li %[pid],0x20; " \
- " andc %[pid],%[msr],%[pid]; mtmsr %[pid];" /* Disable IMMU */ \
- " mfpid %[pid];" /* Save old PID */ \
+ " mfmsr %[msr];" /* Save MSR */
+ " li %[pid],0x20;"
+ " andc %[pid],%[msr],%[pid]; mtmsr %[pid];" /* Disable IMMU */
+ " mfpid %[pid];" /* Save old PID */
" sync; isync;"
- " srwi. %[count],%[len],0x2;" /* How many words? */
- " beq- 2f;" /* No words. Go do bytes */
+ " srwi. %[count],%[len],0x2;" /* How many words? */
+ " beq- 2f;" /* No words. Go do bytes */
" mtctr %[count];"
- "1: mtpid %[pid];sync;"
- " lswi %[tmp],%[kaddr],4;" /* Load kernel word */
- " addi %[kaddr],%[kaddr],0x4;" /* next kaddr word */
+ "1: mtpid %[pid]; sync;"
+#ifdef PPC_IBM403
+ " lswi %[tmp],%[kaddr],4;" /* Load kernel word */
+#else
+ " lwz %[tmp],0(%[kaddr]);"
+#endif
+ " addi %[kaddr],%[kaddr],0x4;" /* next kaddr word */
" sync; isync;"
" mtpid %[ctx]; sync;"
- " stswi %[tmp],%[udaddr],4;" /* Store user word */
- " dcbf 0,%[udaddr];" /* flush cache */
- " addi %[udaddr],%[udaddr],0x4;" /* next udaddr word */
+#ifdef PPC_IBM403
+ " stswi %[tmp],%[udaddr],4;" /* Store user word */
+#else
+ " stw %[tmp],0(%[udaddr]);"
+#endif
+ " dcbst 0,%[udaddr];" /* flush cache */
+ " addi %[udaddr],%[udaddr],0x4;" /* next udaddr word */
" sync; isync;"
- " bdnz 1b;" /* repeat */
+ " bdnz 1b;" /* repeat */
- "2: andi. %[count],%[len],0x3;" /* How many remaining bytes? */
+ "2: andi. %[count],%[len],0x3;" /* How many remaining bytes? */
" addi %[count],%[count],0x1;"
" mtctr %[count];"
- "3: bdz 10f;" /* while count */
- " mtpid %[pid];sync;"
- " lbz %[tmp],0(%[kaddr]);" /* Load kernel byte */
- " addi %[kaddr],%[kaddr],0x1;" /* next kaddr byte */
+ "3: bdz 10f;" /* while count */
+ " mtpid %[pid]; sync;"
+ " lbz %[tmp],0(%[kaddr]);" /* Load kernel byte */
+ " addi %[kaddr],%[kaddr],0x1;" /* next kaddr byte */
" sync; isync;"
" mtpid %[ctx]; sync;"
- " stb %[tmp],0(%[udaddr]);" /* Store user byte */
- " dcbf 0,%[udaddr];" /* flush cache */
+ " stb %[tmp],0(%[udaddr]);" /* Store user byte */
+ " dcbst 0,%[udaddr];" /* flush cache */
" addi %[udaddr],%[udaddr],0x1;"
" sync; isync;"
" b 3b;"
- "10:mtpid %[pid]; mtmsr %[msr]; sync; isync;" /* Restore PID and MSR */
+ "10:mtpid %[pid]; mtmsr %[msr]; sync; isync;"
+ /* Restore PID and MSR */
: [msr] "=&r" (msr), [pid] "=&r" (pid), [tmp] "=&r" (tmp)
- : [udaddr] "b" (udaddr), [ctx] "b" (ctx), [kaddr] "b" (kaddr), [len] "b" (len), [count] "b" (count));
+ : [udaddr] "b" (udaddr), [ctx] "b" (ctx), [kaddr] "b" (kaddr),
+ [len] "b" (len), [count] "b" (count));
curpcb->pcb_onfault = NULL;
return 0;
@@ -616,6 +645,7 @@
return 0;
}
+#if 0
int
badaddr(void *addr, size_t size)
{
@@ -666,6 +696,7 @@
return 0;
}
+#endif
/*
* For now, this only deals with the particular unaligned access case
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