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[src/trunk]: src/sys/arch/arm/sociox more on toward dual descriptor design
details: https://anonhg.NetBSD.org/src/rev/3670ebf95f11
branches: trunk
changeset: 746049:3670ebf95f11
user: nisimura <nisimura%NetBSD.org@localhost>
date: Sat Mar 21 04:35:20 2020 +0000
description:
more on toward dual descriptor design
diffstat:
sys/arch/arm/sociox/if_ave.c | 32 +++++++++++++++-----------------
1 files changed, 15 insertions(+), 17 deletions(-)
diffs (109 lines):
diff -r f360211bb624 -r 3670ebf95f11 sys/arch/arm/sociox/if_ave.c
--- a/sys/arch/arm/sociox/if_ave.c Sat Mar 21 02:32:37 2020 +0000
+++ b/sys/arch/arm/sociox/if_ave.c Sat Mar 21 04:35:20 2020 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: if_ave.c,v 1.4 2020/03/21 01:17:51 nisimura Exp $ */
+/* $NetBSD: if_ave.c,v 1.5 2020/03/21 04:35:20 nisimura Exp $ */
/*-
* Copyright (c) 2020 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_ave.c,v 1.4 2020/03/21 01:17:51 nisimura Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_ave.c,v 1.5 2020/03/21 04:35:20 nisimura Exp $");
#include <sys/param.h>
#include <sys/bus.h>
@@ -125,16 +125,13 @@
#define AVEAFRING 0x0f00 /* entry ring number selector */
#define AVEAFEN 0x0ffc /* entry enable bit vector */
-#ifdef _LP64
#define AVETDB 0x1000 /* 64bit Tx descriptor storage base */
#define AVERDB 0x1c00 /* 64bit Rx descriptor storage base */
-#else
-#define AVETDB 0x1000 /* 32bit Tx descriptor storage base */
-#define AVERDB 0x1800 /* 32bit Rx descriptor storage base */
-#endif
+#define AVE32TDB 0x1000 /* 32bit Tx descriptor storage base */
+#define AVE32RDB 0x1800 /* 32bit Rx descriptor storage base */
/*
- * descriptor size is 12 bytes when _LP64, 8 bytes otherwise.
+ * descriptor size is 12 bytes when 64bit paddr design, 8 bytes otherwise.
* 3KB/24KB split or 64bit paddr Tx/Rx descriptor storage.
* 2KB/16KB split or 32bit paddr Tx/Rx descriptor storage.
*/
@@ -146,6 +143,9 @@
uint32_t r0, r1, r2;
};
+struct tdes32 { uint32_t t0, t1; };
+struct rdes32 { uint32_t r0, r1; };
+
#define T0_OWN (1U<<31) /* desc is ready to Tx */
#define T0_IOC (1U<<29) /* post interrupt on Tx completes */
#define T0_NOCSUM (1U<<28) /* inhibit checksum operation */
@@ -177,7 +177,6 @@
#define AVE_NRXDESC_MASK (AVE_NRXDESC - 1)
#define AVE_NEXTRX(x) (((x) + 1) & AVE_NRXDESC_MASK)
-#ifdef _LP64
#define AVE_INIT_RXDESC(sc, x) \
do { \
struct ave_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \
@@ -189,18 +188,17 @@
__rxd->r1 = htole32(BUS_ADDR_LO32(__paddr)); \
__rxd->r0 = R0_OWN | R0_FL_MASK; \
} while (/*CONSTCOND*/0)
-#else
-#define AVE_INIT_RXDESC(sc, x) \
+
+#define AVE32_INIT_RXDESC(sc, x) \
do { \
struct ave_rxsoft *__rxs = &(sc)->sc_rxsoft[(x)]; \
- struct rdes *__rxd = &(sc)->sc_rxdescs[(x)]; \
+ struct rdes32 *__rxd = &(sc)->sc_rxd32[(x)]; \
struct mbuf *__m = __rxs->rxs_mbuf; \
bus_addr_t __paddr =__rxs->rxs_dmamap->dm_segs[0].ds_addr; \
__m->m_data = __m->m_ext.ext_buf; \
__rxd->r1 = htole32(__paddr); \
__rxd->r0 = R0_OWN | R0_FL_MASK; \
} while (/*CONSTCOND*/0)
-#endif
struct ave_txsoft {
struct mbuf *txs_mbuf; /* head of our mbuf chain */
@@ -236,6 +234,8 @@
struct tdes *sc_txdescs; /* PTR to tdes [NTXDESC] array */
struct rdes *sc_rxdescs; /* PTR to rdes [NRXDESC] array */
+ struct tdes32 *sc_txd32;
+ struct rdes32 *sc_rxd32;
struct ave_txsoft sc_txsoft[AVE_TXQUEUELEN];
struct ave_rxsoft sc_rxsoft[AVE_NRXDESC];
@@ -515,6 +515,8 @@
/* set ptr to Tx/Rx descriptor store */
sc->sc_txdescs = (void *)((uintptr_t)sc->sc_sh + AVETDB);
sc->sc_rxdescs = (void *)((uintptr_t)sc->sc_sh + AVERDB);
+ sc->sc_txd32 = (void *)((uintptr_t)sc->sc_sh + AVE32TDB);
+ sc->sc_rxd32 = (void *)((uintptr_t)sc->sc_sh + AVE32RDB);
/* build sane and loaded Tx/Rx descriptors */
memset(sc->sc_txdescs, 0, sizeof(struct tdes)*AVE_NTXDESC);
@@ -969,12 +971,8 @@
* yet. That could cause a race condition.
* We'll do it below.
*/
-#ifdef _LP64
tdes->t2 = htole32(BUS_ADDR_HI32(paddr));
tdes->t1 = htole32(BUS_ADDR_LO32(paddr));
-#else
- tdes->t1 = htole32(paddr);
-#endif
tdes->t0 = tdes0 | sc->sc_t0csum
| (dmamap->dm_segs[seg].ds_len & T0_TBS_MASK);
tdes0 = T0_OWN; /* 2nd and other segments */
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