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[src/FSF]: src/external/gpl3/binutils/dist/opcodes from ftp.gnu.org
details: https://anonhg.NetBSD.org/src/rev/180ae83b9cca
branches: FSF
changeset: 746646:180ae83b9cca
user: christos <christos%NetBSD.org@localhost>
date: Sun Sep 29 13:48:10 2013 +0000
description:
from ftp.gnu.org
diffstat:
external/gpl3/binutils/dist/opcodes/microblaze-dis.c | 6 +-
external/gpl3/binutils/dist/opcodes/micromips-opc.c | 1143 +
external/gpl3/binutils/dist/opcodes/mips-dis.c | 1448 +-
external/gpl3/binutils/dist/opcodes/mips-opc.c | 535 +-
external/gpl3/binutils/dist/opcodes/mips16-opc.c | 22 +-
external/gpl3/binutils/dist/opcodes/mmix-dis.c | 5 +-
external/gpl3/binutils/dist/opcodes/moxie-dis.c | 5 +-
external/gpl3/binutils/dist/opcodes/msp430-dis.c | 4 +-
external/gpl3/binutils/dist/opcodes/mt-dis.c | 2 +-
external/gpl3/binutils/dist/opcodes/or32-dis.c | 5 +-
external/gpl3/binutils/dist/opcodes/or32-opc.c | 12 +-
external/gpl3/binutils/dist/opcodes/pdp11-dis.c | 32 +-
external/gpl3/binutils/dist/opcodes/pj-dis.c | 5 +-
external/gpl3/binutils/dist/opcodes/po/POTFILES.in | 16 +
external/gpl3/binutils/dist/opcodes/po/da.gmo | Bin
external/gpl3/binutils/dist/opcodes/po/da.po | 1114 +-
external/gpl3/binutils/dist/opcodes/po/es.gmo | Bin
external/gpl3/binutils/dist/opcodes/po/es.po | 680 +-
external/gpl3/binutils/dist/opcodes/po/fi.gmo | Bin
external/gpl3/binutils/dist/opcodes/po/fi.po | 514 +-
external/gpl3/binutils/dist/opcodes/po/it.gmo | Bin
external/gpl3/binutils/dist/opcodes/po/it.po | 1242 ++
external/gpl3/binutils/dist/opcodes/po/opcodes.pot | 500 +-
external/gpl3/binutils/dist/opcodes/po/uk.gmo | Bin
external/gpl3/binutils/dist/opcodes/po/uk.po | 1308 ++
external/gpl3/binutils/dist/opcodes/po/vi.gmo | Bin
external/gpl3/binutils/dist/opcodes/po/vi.po | 798 +-
external/gpl3/binutils/dist/opcodes/ppc-dis.c | 424 +-
external/gpl3/binutils/dist/opcodes/ppc-opc.c | 3886 ++++--
external/gpl3/binutils/dist/opcodes/rl78-decode.c | 5747 +++++++++
external/gpl3/binutils/dist/opcodes/rl78-decode.opc | 1267 ++
external/gpl3/binutils/dist/opcodes/rl78-dis.c | 328 +
external/gpl3/binutils/dist/opcodes/rx-decode.c | 1232 +-
external/gpl3/binutils/dist/opcodes/rx-decode.opc | 20 +-
external/gpl3/binutils/dist/opcodes/rx-dis.c | 4 +-
external/gpl3/binutils/dist/opcodes/s390-dis.c | 4 +-
external/gpl3/binutils/dist/opcodes/s390-opc.c | 219 +-
external/gpl3/binutils/dist/opcodes/s390-opc.txt | 325 +-
external/gpl3/binutils/dist/opcodes/sh-dis.c | 9 +-
external/gpl3/binutils/dist/opcodes/sh64-dis.c | 6 +-
external/gpl3/binutils/dist/opcodes/sparc-dis.c | 36 +-
external/gpl3/binutils/dist/opcodes/sparc-opc.c | 2385 ++-
external/gpl3/binutils/dist/opcodes/spu-dis.c | 4 +-
external/gpl3/binutils/dist/opcodes/sysdep.h | 11 +-
external/gpl3/binutils/dist/opcodes/tic30-dis.c | 4 +-
external/gpl3/binutils/dist/opcodes/tic4x-dis.c | 3 +-
external/gpl3/binutils/dist/opcodes/tic54x-dis.c | 5 +-
external/gpl3/binutils/dist/opcodes/tic80-dis.c | 6 +-
external/gpl3/binutils/dist/opcodes/tic80-opc.c | 5 +-
external/gpl3/binutils/dist/opcodes/tilegx-dis.c | 135 +
external/gpl3/binutils/dist/opcodes/tilegx-opc.c | 8122 +++++++++++++
external/gpl3/binutils/dist/opcodes/tilepro-dis.c | 232 +
external/gpl3/binutils/dist/opcodes/tilepro-opc.c | 10241 +++++++++++++++++
external/gpl3/binutils/dist/opcodes/v850-dis.c | 22 +-
external/gpl3/binutils/dist/opcodes/v850-opc.c | 66 +-
external/gpl3/binutils/dist/opcodes/vax-dis.c | 4 +-
external/gpl3/binutils/dist/opcodes/w65-dis.c | 5 +-
external/gpl3/binutils/dist/opcodes/xgate-dis.c | 396 +
external/gpl3/binutils/dist/opcodes/xgate-opc.c | 204 +
external/gpl3/binutils/dist/opcodes/xtensa-dis.c | 4 +-
external/gpl3/binutils/dist/opcodes/z8k-opc.h | 148 +-
external/gpl3/binutils/dist/opcodes/z8kgen.c | 22 +-
62 files changed, 39491 insertions(+), 5436 deletions(-)
diffs (truncated from 55022 to 300 lines):
diff -r af6b69a2cfa8 -r 180ae83b9cca external/gpl3/binutils/dist/opcodes/microblaze-dis.c
--- a/external/gpl3/binutils/dist/opcodes/microblaze-dis.c Sun Sep 29 13:38:08 2013 +0000
+++ b/external/gpl3/binutils/dist/opcodes/microblaze-dis.c Sun Sep 29 13:48:10 2013 +0000
@@ -1,6 +1,6 @@
/* Disassemble Xilinx microblaze instructions.
- Copyright 2009 Free Software Foundation, Inc.
+ Copyright 2009, 2012 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
@@ -227,7 +227,7 @@
prev_insn_vma = curr_insn_vma;
if (op->name == NULL)
- print_func (stream, ".short 0x%04x", inst);
+ print_func (stream, ".short 0x%04x", (unsigned int) inst);
else
{
print_func (stream, "%s", op->name);
@@ -383,7 +383,7 @@
break;
default:
/* If the disassembler lags the instruction set. */
- print_func (stream, "\tundecoded operands, inst is 0x%04x", inst);
+ print_func (stream, "\tundecoded operands, inst is 0x%04x", (unsigned int) inst);
break;
}
}
diff -r af6b69a2cfa8 -r 180ae83b9cca external/gpl3/binutils/dist/opcodes/micromips-opc.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/external/gpl3/binutils/dist/opcodes/micromips-opc.c Sun Sep 29 13:48:10 2013 +0000
@@ -0,0 +1,1143 @@
+/* micromips-opc.c. microMIPS opcode table.
+ Copyright 2008, 2012 Free Software Foundation, Inc.
+ Contributed by Chao-ying Fu, MIPS Technologies, Inc.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this file; see the file COPYING. If not, write to the
+ Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "opcode/mips.h"
+
+#define UBD INSN_UNCOND_BRANCH_DELAY
+#define CBD INSN_COND_BRANCH_DELAY
+#define NODS INSN_NO_DELAY_SLOT
+#define TRAP INSN_NO_DELAY_SLOT
+#define SM INSN_STORE_MEMORY
+#define BD16 INSN2_BRANCH_DELAY_16BIT /* Used in pinfo2. */
+#define BD32 INSN2_BRANCH_DELAY_32BIT /* Used in pinfo2. */
+
+/* For 16-bit/32-bit microMIPS instructions. They are used in pinfo2. */
+#define UBR INSN2_UNCOND_BRANCH
+#define CBR INSN2_COND_BRANCH
+#define WR_mb INSN2_WRITE_GPR_MB
+#define RD_mc INSN2_READ_GPR_MC
+#define RD_md INSN2_MOD_GPR_MD
+#define WR_md INSN2_MOD_GPR_MD
+#define RD_me INSN2_READ_GPR_ME
+#define RD_mf INSN2_MOD_GPR_MF
+#define WR_mf INSN2_MOD_GPR_MF
+#define RD_mg INSN2_READ_GPR_MG
+#define WR_mhi INSN2_WRITE_GPR_MHI
+#define RD_mj INSN2_READ_GPR_MJ
+#define WR_mj INSN2_WRITE_GPR_MJ
+#define RD_ml RD_mc /* Reuse, since the bit position is the same. */
+#define RD_mmn INSN2_READ_GPR_MMN
+#define RD_mp INSN2_READ_GPR_MP
+#define WR_mp INSN2_WRITE_GPR_MP
+#define RD_mq INSN2_READ_GPR_MQ
+#define RD_sp INSN2_MOD_SP
+#define WR_sp INSN2_MOD_SP
+#define RD_31 INSN2_READ_GPR_31
+#define RD_gp INSN2_READ_GP
+#define RD_pc INSN2_READ_PC
+
+/* For 32-bit microMIPS instructions. */
+#define WR_s INSN_WRITE_GPR_S
+#define WR_d INSN_WRITE_GPR_D
+#define WR_t INSN_WRITE_GPR_T
+#define WR_31 INSN_WRITE_GPR_31
+#define WR_D INSN_WRITE_FPR_D
+#define WR_T INSN_WRITE_FPR_T
+#define WR_S INSN_WRITE_FPR_S
+#define WR_CC INSN_WRITE_COND_CODE
+
+#define RD_s INSN_READ_GPR_S
+#define RD_b INSN_READ_GPR_S
+#define RD_t INSN_READ_GPR_T
+#define RD_T INSN_READ_FPR_T
+#define RD_S INSN_READ_FPR_S
+#define RD_R INSN_READ_FPR_R
+#define RD_D INSN2_READ_FPR_D /* Used in pinfo2. */
+#define RD_CC INSN_READ_COND_CODE
+#define RD_C0 INSN_COP
+#define RD_C1 INSN_COP
+#define RD_C2 INSN_COP
+#define WR_C0 INSN_COP
+#define WR_C1 INSN_COP
+#define WR_C2 INSN_COP
+#define CP INSN_COP
+
+#define WR_HI INSN_WRITE_HI
+#define RD_HI INSN_READ_HI
+
+#define WR_LO INSN_WRITE_LO
+#define RD_LO INSN_READ_LO
+
+#define WR_HILO WR_HI|WR_LO
+#define RD_HILO RD_HI|RD_LO
+#define MOD_HILO WR_HILO|RD_HILO
+
+/* Reuse INSN_ISA1 for 32-bit microMIPS ISA. All instructions in I1
+ are accepted as 32-bit microMIPS ISA.
+ Reuse INSN_ISA3 for 64-bit microMIPS ISA. All instructions in I3
+ are accepted as 64-bit microMIPS ISA. */
+#define I1 INSN_ISA1
+#define I3 INSN_ISA3
+
+/* MIPS DSP ASE support. */
+#define WR_a WR_HILO /* Write DSP accumulators (reuse WR_HILO). */
+#define RD_a RD_HILO /* Read DSP accumulators (reuse RD_HILO). */
+#define MOD_a WR_a|RD_a
+#define DSP_VOLA INSN_NO_DELAY_SLOT
+#define D32 INSN_DSP
+#define D33 INSN_DSPR2
+
+/* MIPS MCU (MicroController) ASE support. */
+#define MC INSN_MCU
+
+const struct mips_opcode micromips_opcodes[] =
+{
+/* These instructions appear first so that the disassembler will find
+ them first. The assemblers uses a hash table based on the
+ instruction name anyhow. */
+/* name, args, match, mask, pinfo, pinfo2, membership, [exclusions] */
+{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_b, 0, I1 },
+{"pref", "k,o(b)", 0, (int) M_PREF_OB, INSN_MACRO, 0, I1 },
+{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1 },
+{"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_b|RD_t|FP_S, 0, I1 },
+{"nop", "", 0x0c00, 0xffff, 0, INSN2_ALIAS, I1 },
+{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
+{"ssnop", "", 0x00000800, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
+{"ehb", "", 0x00001800, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
+{"pause", "", 0x00002800, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
+{"li", "md,mI", 0xec00, 0xfc00, 0, WR_md, I1 },
+{"li", "t,j", 0x30000000, 0xfc1f0000, WR_t, INSN2_ALIAS, I1 }, /* addiu */
+{"li", "t,i", 0x50000000, 0xfc1f0000, WR_t, INSN2_ALIAS, I1 }, /* ori */
+#if 0
+/* Disabled until we can handle 48-bit opcodes. */
+{"li", "s,I", 0x7c0000010000, 0xfc00001f0000, WR_t, 0, I3 }, /* li48 */
+#endif
+{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 },
+{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 },
+{"move", "mp,mj", 0x0c00, 0xfc00, 0, WR_mp|RD_mj, I1 },
+{"move", "d,s", 0x58000150, 0xffe007ff, WR_d|RD_s, INSN2_ALIAS, I3 }, /* daddu */
+{"move", "d,s", 0x00000150, 0xffe007ff, WR_d|RD_s, INSN2_ALIAS, I1 }, /* addu */
+{"move", "d,s", 0x00000290, 0xffe007ff, WR_d|RD_s, INSN2_ALIAS, I1 }, /* or */
+{"b", "mD", 0xcc00, 0xfc00, UBD, 0, I1 },
+{"b", "p", 0x94000000, 0xffff0000, UBD, INSN2_ALIAS, I1 }, /* beq 0, 0 */
+{"b", "p", 0x40400000, 0xffff0000, UBD, INSN2_ALIAS, I1 }, /* bgez 0 */
+{"bal", "p", 0x40600000, 0xffff0000, UBD|WR_31, INSN2_ALIAS|BD32, I1 }, /* bgezal 0 */
+{"bals", "p", 0x42600000, 0xffff0000, UBD|WR_31, INSN2_ALIAS|BD16, I1 }, /* bgezals 0 */
+{"bc", "p", 0x40e00000, 0xffff0000, NODS, INSN2_ALIAS|UBR, I1 }, /* beqzc 0 */
+
+{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
+{"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_T|RD_S|FP_S, 0, I1 },
+{"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_T|RD_S|FP_D, 0, I1 },
+{"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, SM|RD_b|NODS, 0, MC },
+{"aclr", "\\,o(b)", 0, (int) M_ACLR_OB, INSN_MACRO, 0, MC },
+{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, MC },
+{"add", "d,v,t", 0x00000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
+{"add.d", "D,V,T", 0x54000130, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"add.s", "D,V,T", 0x54000030, 0xfc0007ff, WR_D|RD_S|RD_T|FP_S, 0, I1 },
+{"add.ps", "D,V,T", 0x54000230, 0xfc0007ff, WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"addi", "t,r,j", 0x10000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"addiu", "mp,mj,mZ", 0x0c00, 0xfc00, 0, WR_mp|RD_mj, I1 }, /* move */
+{"addiu", "md,ms,mW", 0x6c01, 0xfc01, 0, WR_md|RD_sp, I1 }, /* addiur1sp */
+{"addiu", "md,mc,mB", 0x6c00, 0xfc01, 0, WR_md|RD_mc, I1 }, /* addiur2 */
+{"addiu", "ms,mt,mY", 0x4c01, 0xfc01, 0, WR_sp|RD_sp, I1 }, /* addiusp */
+{"addiu", "mp,mt,mX", 0x4c00, 0xfc01, 0, WR_mp|RD_mp, I1 }, /* addius5 */
+{"addiu", "mb,mr,mQ", 0x78000000, 0xfc000000, 0, WR_mb|RD_pc, I1 }, /* addiupc */
+{"addiu", "t,r,j", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"addiupc", "mb,mQ", 0x78000000, 0xfc000000, 0, WR_mb|RD_pc, I1 },
+{"addiur1sp", "md,mW", 0x6c01, 0xfc01, 0, WR_md|RD_sp, I1 },
+{"addiur2", "md,mc,mB", 0x6c00, 0xfc01, 0, WR_md|RD_mc, I1 },
+{"addiusp", "mY", 0x4c01, 0xfc01, 0, WR_sp|RD_sp, I1 },
+{"addius5", "mp,mX", 0x4c00, 0xfc01, 0, WR_mp|RD_mp, I1 },
+{"addu", "mp,mj,mz", 0x0c00, 0xfc00, 0, WR_mp|RD_mj, I1 }, /* move */
+{"addu", "mp,mz,mj", 0x0c00, 0xfc00, 0, WR_mp|RD_mj, I1 }, /* move */
+{"addu", "md,me,ml", 0x0400, 0xfc01, 0, WR_md|RD_me|RD_ml, I1 },
+{"addu", "d,v,t", 0x00000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 },
+/* We have no flag to mark the read from "y", so we use NODS to disable
+ delay slot scheduling of ALNV.PS altogether. */
+{"alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, NODS|WR_D|RD_S|RD_T|FP_D, 0, I1 },
+{"and", "mf,mt,mg", 0x4480, 0xffc0, 0, WR_mf|RD_mf|RD_mg, I1 },
+{"and", "mf,mg,mx", 0x4480, 0xffc0, 0, WR_mf|RD_mf|RD_mg, I1 },
+{"and", "d,v,t", 0x00000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
+{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 },
+{"andi", "md,mc,mC", 0x2c00, 0xfc00, 0, WR_md|RD_mc, I1 },
+{"andi", "t,r,i", 0xd0000000, 0xfc000000, WR_t|RD_s, 0, I1 },
+{"aset", "\\,~(b)", 0x20003000, 0xff00f000, SM|RD_b|NODS, 0, MC },
+{"aset", "\\,o(b)", 0, (int) M_ASET_OB, INSN_MACRO, 0, MC },
+{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, MC },
+/* b is at the top of the table. */
+/* bal is at the top of the table. */
+{"bc1f", "p", 0x43800000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
+{"bc1f", "N,p", 0x43800000, 0xffe30000, CBD|RD_CC|FP_S, 0, I1 },
+{"bc1fl", "p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"bc1fl", "N,p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"bc2f", "p", 0x42800000, 0xffff0000, CBD|RD_CC, 0, I1 },
+{"bc2f", "N,p", 0x42800000, 0xffe30000, CBD|RD_CC, 0, I1 },
+{"bc2fl", "p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1 },
+{"bc2fl", "N,p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1 },
+{"bc1t", "p", 0x43a00000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
+{"bc1t", "N,p", 0x43a00000, 0xffe30000, CBD|RD_CC|FP_S, 0, I1 },
+{"bc1tl", "p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"bc1tl", "N,p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1 },
+{"bc2t", "p", 0x42a00000, 0xffff0000, CBD|RD_CC, 0, I1 },
+{"bc2t", "N,p", 0x42a00000, 0xffe30000, CBD|RD_CC, 0, I1 },
+{"bc2tl", "p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1 },
+{"bc2tl", "N,p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1 },
+{"beqz", "md,mE", 0x8c00, 0xfc00, CBD, RD_md, I1 },
+{"beqz", "s,p", 0x94000000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"beqzc", "s,p", 0x40e00000, 0xffe00000, NODS|RD_s, CBR, I1 },
+{"beqzl", "s,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1 },
+{"beq", "md,mz,mE", 0x8c00, 0xfc00, CBD, RD_md, I1 }, /* beqz */
+{"beq", "mz,md,mE", 0x8c00, 0xfc00, CBD, RD_md, I1 }, /* beqz */
+{"beq", "s,t,p", 0x94000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
+{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 },
+{"beql", "s,t,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1 },
+{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I1 },
+{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 },
+{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 },
+{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I1 },
+{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I1 },
+{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 },
+{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 },
+{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I1 },
+{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I1 },
+{"bgez", "s,p", 0x40400000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"bgezl", "s,p", 0, (int) M_BGEZL, INSN_MACRO, 0, I1 },
+{"bgezal", "s,p", 0x40600000, 0xffe00000, CBD|RD_s|WR_31, BD32, I1 },
+{"bgezals", "s,p", 0x42600000, 0xffe00000, CBD|RD_s|WR_31, BD16, I1 },
+{"bgezall", "s,p", 0, (int) M_BGEZALL, INSN_MACRO, 0, I1 },
+{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 },
+{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 },
+{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I1 },
+{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I1 },
+{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 },
+{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 },
+{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I1 },
+{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I1 },
+{"bgtz", "s,p", 0x40c00000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"bgtzl", "s,p", 0, (int) M_BGTZL, INSN_MACRO, 0, I1 },
+{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 },
+{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 },
+{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I1 },
+{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I1 },
+{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 },
+{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 },
+{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I1 },
+{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I1 },
+{"blez", "s,p", 0x40800000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"blezl", "s,p", 0, (int) M_BLEZL, INSN_MACRO, 0, I1 },
+{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 },
+{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 },
+{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I1 },
+{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I1 },
+{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 },
+{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 },
+{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I1 },
+{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I1 },
+{"bltz", "s,p", 0x40000000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"bltzl", "s,p", 0, (int) M_BLTZL, INSN_MACRO, 0, I1 },
+{"bltzal", "s,p", 0x40200000, 0xffe00000, CBD|RD_s|WR_31, BD32, I1 },
+{"bltzals", "s,p", 0x42200000, 0xffe00000, CBD|RD_s|WR_31, BD16, I1 },
+{"bltzall", "s,p", 0, (int) M_BLTZALL, INSN_MACRO, 0, I1 },
+{"bnez", "md,mE", 0xac00, 0xfc00, CBD, RD_md, I1 },
+{"bnez", "s,p", 0xb4000000, 0xffe00000, CBD|RD_s, 0, I1 },
+{"bnezc", "s,p", 0x40a00000, 0xffe00000, NODS|RD_s, CBR, I1 },
+{"bnezl", "s,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1 },
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