[src/trunk]: src/sys/arch/mips/mips Fix wrong register usage in mips_fpu_trap():

[tsutsui <tsutsui%NetBSD.org@localhost>]

details:   https://anonhg.NetBSD.org/src/rev/265d345d95d9
branches:  trunk
changeset: 762633:265d345d95d9
user:      tsutsui <tsutsui%NetBSD.org@localhost>
date:      Thu Feb 24 15:52:23 2011 +0000

description:
Fix wrong register usage in mips_fpu_trap():
 - trapframe is the second arg a1, not a3
 - cause is now loaded in a2, not t0 or t3

Fixes kernel panic during tests/lib/libc/ieeefp:
---
tps-count: 4
tp-start: t_except, 6
tc-start: masked_double
pid 645(t_except): trap: cpu0, TLB modification in kernel mode
status=0x2000ff03, cause=0x4, epc=0x80001420, vaddr=0x4026c8
tf=0xc8b15d00 ksp=0xc8b15da0 ra=0x8024af80 ppl=0x7fff5cd0
kernel: TLB modification trap
Stopped in pid 645.1 (t_except) at      \
        netbsd:mips_fpu_intr+0x74:  sw      t3,144(a3)
db>
----
though the ieeefp tests still fail in various places.

diffstat:

 sys/arch/mips/mips/locore.S |  12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diffs (34 lines):

diff -r c9ea74a0a03d -r 265d345d95d9 sys/arch/mips/mips/locore.S
--- a/sys/arch/mips/mips/locore.S       Thu Feb 24 15:47:59 2011 +0000
+++ b/sys/arch/mips/mips/locore.S       Thu Feb 24 15:52:23 2011 +0000
@@ -1,4 +1,4 @@
-/*     $NetBSD: locore.S,v 1.179 2011/02/24 15:27:00 tsutsui Exp $     */
+/*     $NetBSD: locore.S,v 1.180 2011/02/24 15:52:23 tsutsui Exp $     */
 
 /*
  * Copyright (c) 1992, 1993
@@ -653,11 +653,11 @@
 /*
  * Send a floating point exception signal to the current LWP.
  */
-       srl             t0, 8
-       sll             t0, 8
-       ori             t3, T_RES_INST << MIPS_CR_EXC_CODE_SHIFT
+       srl             a2, 8
+       sll             a2, 8
+       ori             a2, T_RES_INST << MIPS_CR_EXC_CODE_SHIFT
        REG_PROLOGUE
-       REG_S           t3, TF_REG_CAUSE(a3)
+       REG_S           a2, TF_REG_CAUSE(a1)
        REG_EPILOGUE
 
        move            a1, a0                          # code = instruction
@@ -673,7 +673,7 @@
  */
 3:
        REG_PROLOGUE
-       REG_S           t3, TF_REG_CAUSE(a3)
+       REG_S           a2, TF_REG_CAUSE(a1)
        REG_EPILOGUE
 
        and             a0, t0, ~MIPS_FPU_EXCEPTION_BITS